2 * linux/arch/arm/mach-pxa/pxa27x.c
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA27x aka Bulverde.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/platform_device.h>
20 #include <asm/hardware.h>
22 #include <asm/arch/irqs.h>
23 #include <asm/arch/pxa-regs.h>
24 #include <asm/arch/pxa2xx-regs.h>
25 #include <asm/arch/ohci.h>
26 #include <asm/arch/pm.h>
27 #include <asm/arch/dma.h>
33 /* Crystal clock: 13MHz */
34 #define BASE_CLK 13000000
37 * Get the clock frequency as reflected by CCSR and the turbo flag.
38 * We assume these values have been applied via a fcs.
39 * If info is not 0 we also display the current settings.
41 unsigned int pxa27x_get_clk_frequency_khz(int info)
43 unsigned long ccsr, clkcfg;
44 unsigned int l, L, m, M, n2, N, S;
48 cccr_a = CCCR & (1 << 25);
50 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
51 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
52 t = clkcfg & (1 << 0);
53 ht = clkcfg & (1 << 2);
54 b = clkcfg & (1 << 3);
58 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
62 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
66 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
67 L / 1000000, (L % 1000000) / 10000, l );
68 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
69 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
71 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
72 M / 1000000, (M % 1000000) / 10000, m );
73 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
74 S / 1000000, (S % 1000000) / 10000 );
77 return (t) ? (N/1000) : (L/1000);
81 * Return the current mem clock frequency in units of 10kHz as
82 * reflected by CCCR[A], B, and L
84 unsigned int pxa27x_get_memclk_frequency_10khz(void)
86 unsigned long ccsr, clkcfg;
87 unsigned int l, L, m, M;
91 cccr_a = CCCR & (1 << 25);
93 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
94 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
95 b = clkcfg & (1 << 3);
98 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
101 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
107 * Return the current LCD clock frequency in units of 10kHz as
109 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
112 unsigned int l, L, k, K;
117 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
125 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
127 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
130 static const struct clkops clk_pxa27x_lcd_ops = {
131 .enable = clk_cken_enable,
132 .disable = clk_cken_disable,
133 .getrate = clk_pxa27x_lcd_getrate,
136 static struct clk pxa27x_clks[] = {
137 INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
138 INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
140 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
141 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
142 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
144 INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
145 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
146 INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
147 INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
148 INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
150 INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
151 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
152 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
154 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
155 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
156 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
159 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
160 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
161 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
162 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
163 INIT_CKEN("IMCLK", IM, 0, 0, NULL),
164 INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
170 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
171 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
173 #define RESTORE_GPLEVEL(n) do { \
174 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
175 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
179 * List of global PXA peripheral registers to preserve.
180 * More ones like CP and general purpose register values are preserved
181 * with the stack pointer in sleep.S.
183 enum { SLEEP_SAVE_START = 0,
185 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
186 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
187 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
188 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
189 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
191 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
192 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
193 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
194 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
202 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
203 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
208 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
210 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
211 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
212 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
213 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
214 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
216 SAVE(GAFR0_L); SAVE(GAFR0_U);
217 SAVE(GAFR1_L); SAVE(GAFR1_U);
218 SAVE(GAFR2_L); SAVE(GAFR2_U);
219 SAVE(GAFR3_L); SAVE(GAFR3_U);
222 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
223 SAVE(PFER); SAVE(PKWR);
225 SAVE(ICMR); ICMR = 0;
229 /* Clear GPIO transition detect bits */
230 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
233 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
235 /* ensure not to come back here if it wasn't intended */
238 /* restore registers */
239 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
240 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
241 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
242 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
243 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
244 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
245 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
246 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
247 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
248 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
251 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
252 RESTORE(PFER); RESTORE(PKWR);
254 PSSR = PSSR_RDH | PSSR_PH;
264 void pxa27x_cpu_pm_enter(suspend_state_t state)
266 extern void pxa_cpu_standby(void);
268 if (state == PM_SUSPEND_STANDBY)
269 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
270 (1 << CKEN_LCD) | (1 << CKEN_PWM0);
272 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
274 /* ensure voltage-change sequencer not initiated, which hangs */
277 /* Clear edge-detect status register. */
281 case PM_SUSPEND_STANDBY:
285 /* set resume return address */
286 PSPR = virt_to_phys(pxa_cpu_resume);
287 pxa27x_cpu_suspend(PWRMODE_SLEEP);
292 static int pxa27x_cpu_pm_valid(suspend_state_t state)
294 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
297 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
298 .save_size = SLEEP_SAVE_SIZE,
299 .save = pxa27x_cpu_pm_save,
300 .restore = pxa27x_cpu_pm_restore,
301 .valid = pxa27x_cpu_pm_valid,
302 .enter = pxa27x_cpu_pm_enter,
305 static void __init pxa27x_init_pm(void)
307 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
310 static inline void pxa27x_init_pm(void) {}
313 /* PXA27x: Various gpios can issue wakeup events. This logic only
314 * handles the simple cases, not the WEMUX2 and WEMUX3 options
316 #define PXA27x_GPIO_NOWAKE_MASK \
317 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
318 #define WAKEMASK(gpio) \
320 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
321 : ((gpio == 35) ? (1 << 24) : 0))
323 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
325 int gpio = IRQ_TO_GPIO(irq);
328 if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
329 if (WAKEMASK(gpio) == 0)
332 mask = WAKEMASK(gpio);
335 if (GRER(gpio) | GPIO_bit(gpio))
340 if (GFER(gpio) | GPIO_bit(gpio))
368 void __init pxa27x_init_irq(void)
372 pxa_init_irq_gpio(128);
373 pxa_init_irq_set_wake(pxa27x_set_wake);
377 * device registration specific to PXA27x.
380 static struct resource i2c_power_resources[] = {
384 .flags = IORESOURCE_MEM,
388 .flags = IORESOURCE_IRQ,
392 struct platform_device pxa27x_device_i2c_power = {
393 .name = "pxa2xx-i2c",
395 .resource = i2c_power_resources,
396 .num_resources = ARRAY_SIZE(i2c_power_resources),
399 static struct platform_device *devices[] __initdata = {
406 &pxa27x_device_i2c_power,
412 static int __init pxa27x_init(void)
415 if (cpu_is_pxa27x()) {
416 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
418 if ((ret = pxa_init_dma(32)))
423 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
428 subsys_initcall(pxa27x_init);