2 * linux/arch/arm/mach-pxa/pxa25x.c
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA21x/25x/26x variants.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/sysdev.h>
26 #include <asm/hardware.h>
27 #include <asm/arch/irqs.h>
28 #include <asm/arch/pxa-regs.h>
29 #include <asm/arch/mfp-pxa25x.h>
30 #include <asm/arch/pm.h>
31 #include <asm/arch/dma.h>
38 * Various clock factors driven by the CCCR register.
41 /* Crystal Frequency to Memory Frequency Multiplier (L) */
42 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
44 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
45 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
47 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
48 /* Note: we store the value N * 2 here. */
49 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
52 #define BASE_CLK 3686400
55 * Get the clock frequency as reflected by CCCR and the turbo flag.
56 * We assume these values have been applied via a fcs.
57 * If info is not 0 we also display the current settings.
59 unsigned int pxa25x_get_clk_frequency_khz(int info)
61 unsigned long cccr, turbo;
62 unsigned int l, L, m, M, n2, N;
65 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
67 l = L_clk_mult[(cccr >> 0) & 0x1f];
68 m = M_clk_mult[(cccr >> 5) & 0x03];
69 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
78 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
79 L / 1000000, (L % 1000000) / 10000, l );
81 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
82 M / 1000000, (M % 1000000) / 10000, m );
84 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
85 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
86 (turbo & 1) ? "" : "in" );
89 return (turbo & 1) ? (N/1000) : (M/1000);
93 * Return the current memory clock frequency in units of 10kHz
95 unsigned int pxa25x_get_memclk_frequency_10khz(void)
97 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
100 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
102 return pxa25x_get_memclk_frequency_10khz() * 10000;
105 static const struct clkops clk_pxa25x_lcd_ops = {
106 .enable = clk_cken_enable,
107 .disable = clk_cken_disable,
108 .getrate = clk_pxa25x_lcd_getrate,
112 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
113 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
114 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
116 static struct clk pxa25x_hwuart_clk =
117 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
120 static struct clk pxa25x_clks[] = {
121 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
122 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
123 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
124 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
125 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
126 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
127 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
129 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
130 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
131 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
133 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
136 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
137 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
138 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
140 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
145 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
146 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
149 * List of global PXA peripheral registers to preserve.
150 * More ones like CP and general purpose register values are preserved
151 * with the stack pointer in sleep.S.
153 enum { SLEEP_SAVE_START = 0,
155 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
157 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
158 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
159 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
169 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
171 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
173 SAVE(GAFR0_L); SAVE(GAFR0_U);
174 SAVE(GAFR1_L); SAVE(GAFR1_U);
175 SAVE(GAFR2_L); SAVE(GAFR2_U);
180 /* Clear GPIO transition detect bits */
181 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
184 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
186 /* ensure not to come back here if it wasn't intended */
189 /* restore registers */
190 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
191 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
192 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
193 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
195 PSSR = PSSR_RDH | PSSR_PH;
201 static void pxa25x_cpu_pm_enter(suspend_state_t state)
205 /* set resume return address */
206 PSPR = virt_to_phys(pxa_cpu_resume);
207 pxa25x_cpu_suspend(PWRMODE_SLEEP);
212 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
213 .save_size = SLEEP_SAVE_SIZE,
214 .valid = suspend_valid_only_mem,
215 .save = pxa25x_cpu_pm_save,
216 .restore = pxa25x_cpu_pm_restore,
217 .enter = pxa25x_cpu_pm_enter,
220 static void __init pxa25x_init_pm(void)
222 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
225 static inline void pxa25x_init_pm(void) {}
228 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
231 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
233 int gpio = IRQ_TO_GPIO(irq);
236 if (gpio >= 0 && gpio < 85)
237 return gpio_set_wake(gpio, on);
239 if (irq == IRQ_RTCAlrm) {
255 void __init pxa25x_init_irq(void)
257 pxa_init_irq(32, pxa25x_set_wake);
258 pxa_init_gpio(85, pxa25x_set_wake);
261 static struct platform_device *pxa25x_devices[] __initdata = {
273 static struct sys_device pxa25x_sysdev[] = {
275 .cls = &pxa_irq_sysclass,
277 .cls = &pxa_gpio_sysclass,
281 static int __init pxa25x_init(void)
285 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
287 clks_register(&pxa25x_hwuart_clk, 1);
289 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
290 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
292 if ((ret = pxa_init_dma(16)))
297 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
298 ret = sysdev_register(&pxa25x_sysdev[i]);
300 pr_err("failed to register sysdev[%d]\n", i);
303 ret = platform_add_devices(pxa25x_devices,
304 ARRAY_SIZE(pxa25x_devices));
309 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
311 ret = platform_device_register(&pxa_device_hwuart);
316 postcore_initcall(pxa25x_init);