2 * linux/arch/arm/mach-pxa/gpio.c
4 * Generic PXA GPIO handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/irq.h>
20 #include <asm/hardware.h>
22 #include <asm/arch/pxa-regs.h>
27 struct pxa_gpio_chip {
28 struct gpio_chip chip;
29 void __iomem *regbase;
35 * Configure pins for GPIO or other functions
37 int pxa_gpio_mode(int gpio_mode)
40 int gpio = gpio_mode & GPIO_MD_MASK_NR;
41 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
44 if (gpio > pxa_last_gpio)
47 local_irq_save(flags);
48 if (gpio_mode & GPIO_DFLT_LOW)
49 GPCR(gpio) = GPIO_bit(gpio);
50 else if (gpio_mode & GPIO_DFLT_HIGH)
51 GPSR(gpio) = GPIO_bit(gpio);
52 if (gpio_mode & GPIO_MD_MASK_DIR)
53 GPDR(gpio) |= GPIO_bit(gpio);
55 GPDR(gpio) &= ~GPIO_bit(gpio);
56 gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
57 GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
58 local_irq_restore(flags);
62 EXPORT_SYMBOL(pxa_gpio_mode);
64 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
67 u32 mask = 1 << offset;
69 struct pxa_gpio_chip *pxa;
72 pxa = container_of(chip, struct pxa_gpio_chip, chip);
73 gpdr = pxa->regbase + GPDR_OFFSET;
74 local_irq_save(flags);
75 value = __raw_readl(gpdr);
77 __raw_writel(value, gpdr);
78 local_irq_restore(flags);
83 static int pxa_gpio_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
87 u32 mask = 1 << offset;
89 struct pxa_gpio_chip *pxa;
92 pxa = container_of(chip, struct pxa_gpio_chip, chip);
94 pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
95 gpdr = pxa->regbase + GPDR_OFFSET;
96 local_irq_save(flags);
97 tmp = __raw_readl(gpdr);
99 __raw_writel(tmp, gpdr);
100 local_irq_restore(flags);
108 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
110 u32 mask = 1 << offset;
111 struct pxa_gpio_chip *pxa;
113 pxa = container_of(chip, struct pxa_gpio_chip, chip);
114 return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
118 * Set output GPIO level
120 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122 u32 mask = 1 << offset;
123 struct pxa_gpio_chip *pxa;
125 pxa = container_of(chip, struct pxa_gpio_chip, chip);
128 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
130 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
133 #define GPIO_CHIP(_n) \
135 .regbase = GPIO##_n##_BASE, \
137 .label = "gpio-" #_n, \
138 .direction_input = pxa_gpio_direction_input, \
139 .direction_output = pxa_gpio_direction_output, \
140 .get = pxa_gpio_get, \
141 .set = pxa_gpio_set, \
147 static struct pxa_gpio_chip pxa_gpio_chip[] = {
151 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
157 * PXA GPIO edge detection for IRQs:
158 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
159 * Use this instead of directly setting GRER/GFER.
162 static long GPIO_IRQ_rising_edge[4];
163 static long GPIO_IRQ_falling_edge[4];
164 static long GPIO_IRQ_mask[4];
166 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
170 gpio = IRQ_TO_GPIO(irq);
173 if (type == IRQ_TYPE_PROBE) {
174 /* Don't mess with enabled GPIOs using preconfigured edges or
175 * GPIOs set to alternate function or to output during probe
177 if ((GPIO_IRQ_rising_edge[idx] |
178 GPIO_IRQ_falling_edge[idx] |
179 GPDR(gpio)) & GPIO_bit(gpio))
181 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
183 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
186 pxa_gpio_mode(gpio | GPIO_IN);
188 if (type & IRQ_TYPE_EDGE_RISING)
189 __set_bit(gpio, GPIO_IRQ_rising_edge);
191 __clear_bit(gpio, GPIO_IRQ_rising_edge);
193 if (type & IRQ_TYPE_EDGE_FALLING)
194 __set_bit(gpio, GPIO_IRQ_falling_edge);
196 __clear_bit(gpio, GPIO_IRQ_falling_edge);
198 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
199 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
201 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
202 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
203 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
208 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
211 static void pxa_ack_low_gpio(unsigned int irq)
213 GEDR0 = (1 << (irq - IRQ_GPIO0));
216 static void pxa_mask_low_gpio(unsigned int irq)
218 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
221 static void pxa_unmask_low_gpio(unsigned int irq)
223 ICMR |= 1 << (irq - PXA_IRQ(0));
226 static struct irq_chip pxa_low_gpio_chip = {
228 .ack = pxa_ack_low_gpio,
229 .mask = pxa_mask_low_gpio,
230 .unmask = pxa_unmask_low_gpio,
231 .set_type = pxa_gpio_irq_type,
235 * Demux handler for GPIO>=2 edge detect interrupts
238 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
240 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
243 unsigned long gedr[4];
246 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
247 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
248 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
249 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
251 GEDR0 = gedr[0]; GEDR1 = gedr[1];
252 GEDR2 = gedr[2]; GEDR3 = gedr[3];
255 bit = find_first_bit(gedr, GEDR_BITS);
256 while (bit < GEDR_BITS) {
259 n = PXA_GPIO_IRQ_BASE + bit;
260 desc_handle_irq(n, irq_desc + n);
262 bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
267 static void pxa_ack_muxed_gpio(unsigned int irq)
269 int gpio = irq - IRQ_GPIO(2) + 2;
270 GEDR(gpio) = GPIO_bit(gpio);
273 static void pxa_mask_muxed_gpio(unsigned int irq)
275 int gpio = irq - IRQ_GPIO(2) + 2;
276 __clear_bit(gpio, GPIO_IRQ_mask);
277 GRER(gpio) &= ~GPIO_bit(gpio);
278 GFER(gpio) &= ~GPIO_bit(gpio);
281 static void pxa_unmask_muxed_gpio(unsigned int irq)
283 int gpio = irq - IRQ_GPIO(2) + 2;
285 __set_bit(gpio, GPIO_IRQ_mask);
286 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
287 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
290 static struct irq_chip pxa_muxed_gpio_chip = {
292 .ack = pxa_ack_muxed_gpio,
293 .mask = pxa_mask_muxed_gpio,
294 .unmask = pxa_unmask_muxed_gpio,
295 .set_type = pxa_gpio_irq_type,
298 void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
302 pxa_last_gpio = gpio_nr - 1;
304 /* clear all GPIO edge detects */
305 for (i = 0; i < gpio_nr; i += 32) {
311 /* GPIO 0 and 1 must have their mask bit always set */
312 GPIO_IRQ_mask[0] = 3;
314 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
315 set_irq_chip(irq, &pxa_low_gpio_chip);
316 set_irq_handler(irq, handle_edge_irq);
317 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
320 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
321 set_irq_chip(irq, &pxa_muxed_gpio_chip);
322 set_irq_handler(irq, handle_edge_irq);
323 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
326 /* Install handler for GPIO>=2 edge detect interrupts */
327 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
329 pxa_low_gpio_chip.set_wake = fn;
330 pxa_muxed_gpio_chip.set_wake = fn;
332 /* add a GPIO chip for each register bank.
333 * the last PXA25x register only contains 21 GPIOs
335 for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
336 if (gpio + 32 > gpio_nr)
337 pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
338 gpiochip_add(&pxa_gpio_chip[i].chip);