2 * arch/arm/mach-orion/irq.c
4 * Core IRQ functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
17 #include <asm/arch/orion.h>
18 #include <asm/plat-orion/irq.h>
21 /*****************************************************************************
24 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
25 * value of the line or the opposite value.
27 * Level IRQ handlers: DATA_IN is used directly as cause register.
28 * Interrupt are masked by LEVEL_MASK registers.
29 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
30 * Interrupt are masked by EDGE_MASK registers.
31 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
32 * the polarity to catch the next line transaction.
33 * This is a race condition that might not perfectly
34 * work on some use cases.
36 * Every eight GPIO lines are grouped (OR'ed) before going up to main
40 * data-in /--------| |-----| |----\
41 * -----| |----- ---- to main cause reg
42 * X \----------------| |----/
45 ****************************************************************************/
46 static void orion_gpio_irq_ack(u32 irq)
48 int pin = irq_to_gpio(irq);
49 if (irq_desc[irq].status & IRQ_LEVEL)
51 * Mask bit for level interrupt
53 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
56 * Clear casue bit for egde interrupt
58 orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
61 static void orion_gpio_irq_mask(u32 irq)
63 int pin = irq_to_gpio(irq);
64 if (irq_desc[irq].status & IRQ_LEVEL)
65 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
67 orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
70 static void orion_gpio_irq_unmask(u32 irq)
72 int pin = irq_to_gpio(irq);
73 if (irq_desc[irq].status & IRQ_LEVEL)
74 orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
76 orion_setbits(GPIO_EDGE_MASK, 1 << pin);
79 static int orion_gpio_set_irq_type(u32 irq, u32 type)
81 int pin = irq_to_gpio(irq);
82 struct irq_desc *desc;
84 if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
85 printk(KERN_ERR "orion_gpio_set_irq_type failed "
86 "(irq %d, pin %d).\n", irq, pin);
90 desc = irq_desc + irq;
94 desc->handle_irq = handle_level_irq;
95 desc->status |= IRQ_LEVEL;
96 orion_clrbits(GPIO_IN_POL, (1 << pin));
99 desc->handle_irq = handle_level_irq;
100 desc->status |= IRQ_LEVEL;
101 orion_setbits(GPIO_IN_POL, (1 << pin));
104 desc->handle_irq = handle_edge_irq;
105 desc->status &= ~IRQ_LEVEL;
106 orion_clrbits(GPIO_IN_POL, (1 << pin));
109 desc->handle_irq = handle_edge_irq;
110 desc->status &= ~IRQ_LEVEL;
111 orion_setbits(GPIO_IN_POL, (1 << pin));
114 desc->handle_irq = handle_edge_irq;
115 desc->status &= ~IRQ_LEVEL;
117 * set initial polarity based on current input level
119 if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
121 orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
123 orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
127 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
131 desc->status &= ~IRQ_TYPE_SENSE_MASK;
132 desc->status |= type & IRQ_TYPE_SENSE_MASK;
137 static struct irq_chip orion_gpio_irq_chip = {
138 .name = "Orion-IRQ-GPIO",
139 .ack = orion_gpio_irq_ack,
140 .mask = orion_gpio_irq_mask,
141 .unmask = orion_gpio_irq_unmask,
142 .set_type = orion_gpio_set_irq_type,
145 static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
147 u32 cause, offs, pin;
149 BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
150 offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
151 cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
152 (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
154 for (pin = offs; pin < offs + 8; pin++) {
155 if (cause & (1 << pin)) {
156 irq = gpio_to_irq(pin);
157 desc = irq_desc + irq;
158 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
159 /* Swap polarity (race with GPIO line) */
160 u32 polarity = orion_read(GPIO_IN_POL);
161 polarity ^= 1 << pin;
162 orion_write(GPIO_IN_POL, polarity);
164 desc_handle_irq(irq, desc);
169 static void __init orion_init_gpio_irq(void)
172 struct irq_desc *desc;
175 * Mask and clear GPIO IRQ interrupts
177 orion_write(GPIO_LEVEL_MASK, 0x0);
178 orion_write(GPIO_EDGE_MASK, 0x0);
179 orion_write(GPIO_EDGE_CAUSE, 0x0);
182 * Register chained level handlers for GPIO IRQs by default.
183 * User can use set_type() if he wants to use edge types handlers.
185 for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
186 set_irq_chip(i, &orion_gpio_irq_chip);
187 set_irq_handler(i, handle_level_irq);
189 desc->status |= IRQ_LEVEL;
190 set_irq_flags(i, IRQF_VALID);
192 set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
193 set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
195 set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
198 /*****************************************************************************
200 ****************************************************************************/
201 static void __init orion_init_main_irq(void)
203 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
206 void __init orion_init_irq(void)
208 orion_init_main_irq();
209 orion_init_gpio_irq();