1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
5 * OMAP2/3 PRCM base and module definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 /* Module offsets from both CM_BASE & PRM_BASE */
21 * Offsets that are the same on 24xx and 34xx
23 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
24 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
28 #define CORE_MOD 0x200
30 #define WKUP_MOD 0x400
34 /* Chip-specific module offsets */
35 #define OMAP24XX_DSP_MOD 0x800
37 #define OMAP2430_MDM_MOD 0xc00
39 /* IVA2 module is < base on 3430 */
40 #define OMAP3430_IVA2_MOD -0x800
41 #define OMAP3430ES2_SGX_MOD GFX_MOD
42 #define OMAP3430_CCR_MOD PLL_MOD
43 #define OMAP3430_DSS_MOD 0x600
44 #define OMAP3430_CAM_MOD 0x700
45 #define OMAP3430_PER_MOD 0x800
46 #define OMAP3430_EMU_MOD 0x900
47 #define OMAP3430_GR_MOD 0xa00
48 #define OMAP3430_NEON_MOD 0xb00
49 #define OMAP3430ES2_USBHOST_MOD 0xc00
52 /* 24XX register bits shared between CM & PRM registers */
54 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
55 #define OMAP2420_EN_MMC_SHIFT 26
56 #define OMAP2420_EN_MMC (1 << 26)
57 #define OMAP24XX_EN_UART2_SHIFT 22
58 #define OMAP24XX_EN_UART2 (1 << 22)
59 #define OMAP24XX_EN_UART1_SHIFT 21
60 #define OMAP24XX_EN_UART1 (1 << 21)
61 #define OMAP24XX_EN_MCSPI2_SHIFT 18
62 #define OMAP24XX_EN_MCSPI2 (1 << 18)
63 #define OMAP24XX_EN_MCSPI1_SHIFT 17
64 #define OMAP24XX_EN_MCSPI1 (1 << 17)
65 #define OMAP24XX_EN_MCBSP2_SHIFT 16
66 #define OMAP24XX_EN_MCBSP2 (1 << 16)
67 #define OMAP24XX_EN_MCBSP1_SHIFT 15
68 #define OMAP24XX_EN_MCBSP1 (1 << 15)
69 #define OMAP24XX_EN_GPT12_SHIFT 14
70 #define OMAP24XX_EN_GPT12 (1 << 14)
71 #define OMAP24XX_EN_GPT11_SHIFT 13
72 #define OMAP24XX_EN_GPT11 (1 << 13)
73 #define OMAP24XX_EN_GPT10_SHIFT 12
74 #define OMAP24XX_EN_GPT10 (1 << 12)
75 #define OMAP24XX_EN_GPT9_SHIFT 11
76 #define OMAP24XX_EN_GPT9 (1 << 11)
77 #define OMAP24XX_EN_GPT8_SHIFT 10
78 #define OMAP24XX_EN_GPT8 (1 << 10)
79 #define OMAP24XX_EN_GPT7_SHIFT 9
80 #define OMAP24XX_EN_GPT7 (1 << 9)
81 #define OMAP24XX_EN_GPT6_SHIFT 8
82 #define OMAP24XX_EN_GPT6 (1 << 8)
83 #define OMAP24XX_EN_GPT5_SHIFT 7
84 #define OMAP24XX_EN_GPT5 (1 << 7)
85 #define OMAP24XX_EN_GPT4_SHIFT 6
86 #define OMAP24XX_EN_GPT4 (1 << 6)
87 #define OMAP24XX_EN_GPT3_SHIFT 5
88 #define OMAP24XX_EN_GPT3 (1 << 5)
89 #define OMAP24XX_EN_GPT2_SHIFT 4
90 #define OMAP24XX_EN_GPT2 (1 << 4)
91 #define OMAP2420_EN_VLYNQ_SHIFT 3
92 #define OMAP2420_EN_VLYNQ (1 << 3)
94 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
95 #define OMAP2430_EN_GPIO5_SHIFT 10
96 #define OMAP2430_EN_GPIO5 (1 << 10)
97 #define OMAP2430_EN_MCSPI3_SHIFT 9
98 #define OMAP2430_EN_MCSPI3 (1 << 9)
99 #define OMAP2430_EN_MMCHS2_SHIFT 8
100 #define OMAP2430_EN_MMCHS2 (1 << 8)
101 #define OMAP2430_EN_MMCHS1_SHIFT 7
102 #define OMAP2430_EN_MMCHS1 (1 << 7)
103 #define OMAP24XX_EN_UART3_SHIFT 2
104 #define OMAP24XX_EN_UART3 (1 << 2)
105 #define OMAP24XX_EN_USB_SHIFT 0
106 #define OMAP24XX_EN_USB (1 << 0)
108 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
109 #define OMAP2430_EN_MDM_INTC_SHIFT 11
110 #define OMAP2430_EN_MDM_INTC (1 << 11)
111 #define OMAP2430_EN_USBHS_SHIFT 6
112 #define OMAP2430_EN_USBHS (1 << 6)
114 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
115 #define OMAP2420_ST_MMC (1 << 26)
116 #define OMAP24XX_ST_UART2 (1 << 22)
117 #define OMAP24XX_ST_UART1 (1 << 21)
118 #define OMAP24XX_ST_MCSPI2 (1 << 18)
119 #define OMAP24XX_ST_MCSPI1 (1 << 17)
120 #define OMAP24XX_ST_GPT12 (1 << 14)
121 #define OMAP24XX_ST_GPT11 (1 << 13)
122 #define OMAP24XX_ST_GPT10 (1 << 12)
123 #define OMAP24XX_ST_GPT9 (1 << 11)
124 #define OMAP24XX_ST_GPT8 (1 << 10)
125 #define OMAP24XX_ST_GPT7 (1 << 9)
126 #define OMAP24XX_ST_GPT6 (1 << 8)
127 #define OMAP24XX_ST_GPT5 (1 << 7)
128 #define OMAP24XX_ST_GPT4 (1 << 6)
129 #define OMAP24XX_ST_GPT3 (1 << 5)
130 #define OMAP24XX_ST_GPT2 (1 << 4)
131 #define OMAP2420_ST_VLYNQ (1 << 3)
133 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
134 #define OMAP2430_ST_MDM_INTC (1 << 11)
135 #define OMAP2430_ST_GPIO5 (1 << 10)
136 #define OMAP2430_ST_MCSPI3 (1 << 9)
137 #define OMAP2430_ST_MMCHS2 (1 << 8)
138 #define OMAP2430_ST_MMCHS1 (1 << 7)
139 #define OMAP2430_ST_USBHS (1 << 6)
140 #define OMAP24XX_ST_UART3 (1 << 2)
141 #define OMAP24XX_ST_USB (1 << 0)
143 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
144 #define OMAP24XX_EN_GPIOS_SHIFT 2
145 #define OMAP24XX_EN_GPIOS (1 << 2)
146 #define OMAP24XX_EN_GPT1_SHIFT 0
147 #define OMAP24XX_EN_GPT1 (1 << 0)
149 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
150 #define OMAP24XX_ST_GPIOS (1 << 2)
151 #define OMAP24XX_ST_GPT1 (1 << 0)
153 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
154 #define OMAP2430_ST_MDM (1 << 0)
157 /* 3430 register bits shared between CM & PRM registers */
159 /* CM_REVISION, PRM_REVISION shared bits */
160 #define OMAP3430_REV_SHIFT 0
161 #define OMAP3430_REV_MASK (0xff << 0)
163 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
164 #define OMAP3430_AUTOIDLE (1 << 0)
166 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
167 #define OMAP3430_EN_MMC2 (1 << 25)
168 #define OMAP3430_EN_MMC2_SHIFT 25
169 #define OMAP3430_EN_MMC1 (1 << 24)
170 #define OMAP3430_EN_MMC1_SHIFT 24
171 #define OMAP3430_EN_MCSPI4 (1 << 21)
172 #define OMAP3430_EN_MCSPI4_SHIFT 21
173 #define OMAP3430_EN_MCSPI3 (1 << 20)
174 #define OMAP3430_EN_MCSPI3_SHIFT 20
175 #define OMAP3430_EN_MCSPI2 (1 << 19)
176 #define OMAP3430_EN_MCSPI2_SHIFT 19
177 #define OMAP3430_EN_MCSPI1 (1 << 18)
178 #define OMAP3430_EN_MCSPI1_SHIFT 18
179 #define OMAP3430_EN_I2C3 (1 << 17)
180 #define OMAP3430_EN_I2C3_SHIFT 17
181 #define OMAP3430_EN_I2C2 (1 << 16)
182 #define OMAP3430_EN_I2C2_SHIFT 16
183 #define OMAP3430_EN_I2C1 (1 << 15)
184 #define OMAP3430_EN_I2C1_SHIFT 15
185 #define OMAP3430_EN_UART2 (1 << 14)
186 #define OMAP3430_EN_UART2_SHIFT 14
187 #define OMAP3430_EN_UART1 (1 << 13)
188 #define OMAP3430_EN_UART1_SHIFT 13
189 #define OMAP3430_EN_GPT11 (1 << 12)
190 #define OMAP3430_EN_GPT11_SHIFT 12
191 #define OMAP3430_EN_GPT10 (1 << 11)
192 #define OMAP3430_EN_GPT10_SHIFT 11
193 #define OMAP3430_EN_MCBSP5 (1 << 10)
194 #define OMAP3430_EN_MCBSP5_SHIFT 10
195 #define OMAP3430_EN_MCBSP1 (1 << 9)
196 #define OMAP3430_EN_MCBSP1_SHIFT 9
197 #define OMAP3430_EN_FSHOSTUSB (1 << 5)
198 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5
199 #define OMAP3430_EN_D2D (1 << 3)
200 #define OMAP3430_EN_D2D_SHIFT 3
202 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
203 #define OMAP3430_EN_HSOTGUSB (1 << 4)
204 #define OMAP3430_EN_HSOTGUSB_SHIFT 4
206 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
207 #define OMAP3430_ST_MMC2 (1 << 25)
208 #define OMAP3430_ST_MMC1 (1 << 24)
209 #define OMAP3430_ST_MCSPI4 (1 << 21)
210 #define OMAP3430_ST_MCSPI3 (1 << 20)
211 #define OMAP3430_ST_MCSPI2 (1 << 19)
212 #define OMAP3430_ST_MCSPI1 (1 << 18)
213 #define OMAP3430_ST_I2C3 (1 << 17)
214 #define OMAP3430_ST_I2C2 (1 << 16)
215 #define OMAP3430_ST_I2C1 (1 << 15)
216 #define OMAP3430_ST_UART2 (1 << 14)
217 #define OMAP3430_ST_UART1 (1 << 13)
218 #define OMAP3430_ST_GPT11 (1 << 12)
219 #define OMAP3430_ST_GPT10 (1 << 11)
220 #define OMAP3430_ST_MCBSP5 (1 << 10)
221 #define OMAP3430_ST_MCBSP1 (1 << 9)
222 #define OMAP3430_ST_FSHOSTUSB (1 << 5)
223 #define OMAP3430_ST_HSOTGUSB (1 << 4)
224 #define OMAP3430_ST_D2D (1 << 3)
226 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
227 #define OMAP3430_EN_GPIO1 (1 << 3)
228 #define OMAP3430_EN_GPIO1_SHIFT 3
229 #define OMAP3430_EN_GPT1 (1 << 0)
230 #define OMAP3430_EN_GPT1_SHIFT 0
232 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
233 #define OMAP3430_EN_SR2 (1 << 7)
234 #define OMAP3430_EN_SR2_SHIFT 7
235 #define OMAP3430_EN_SR1 (1 << 6)
236 #define OMAP3430_EN_SR1_SHIFT 6
238 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
239 #define OMAP3430_EN_GPT12 (1 << 1)
240 #define OMAP3430_EN_GPT12_SHIFT 1
242 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
243 #define OMAP3430_ST_SR2 (1 << 7)
244 #define OMAP3430_ST_SR1 (1 << 6)
245 #define OMAP3430_ST_GPIO1 (1 << 3)
246 #define OMAP3430_ST_GPT12 (1 << 1)
247 #define OMAP3430_ST_GPT1 (1 << 0)
250 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
251 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
252 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
254 #define OMAP3430_EN_MPU (1 << 1)
255 #define OMAP3430_EN_MPU_SHIFT 1
257 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
258 #define OMAP3430_EN_GPIO6 (1 << 17)
259 #define OMAP3430_EN_GPIO6_SHIFT 17
260 #define OMAP3430_EN_GPIO5 (1 << 16)
261 #define OMAP3430_EN_GPIO5_SHIFT 16
262 #define OMAP3430_EN_GPIO4 (1 << 15)
263 #define OMAP3430_EN_GPIO4_SHIFT 15
264 #define OMAP3430_EN_GPIO3 (1 << 14)
265 #define OMAP3430_EN_GPIO3_SHIFT 14
266 #define OMAP3430_EN_GPIO2 (1 << 13)
267 #define OMAP3430_EN_GPIO2_SHIFT 13
268 #define OMAP3430_EN_UART3 (1 << 11)
269 #define OMAP3430_EN_UART3_SHIFT 11
270 #define OMAP3430_EN_GPT9 (1 << 10)
271 #define OMAP3430_EN_GPT9_SHIFT 10
272 #define OMAP3430_EN_GPT8 (1 << 9)
273 #define OMAP3430_EN_GPT8_SHIFT 9
274 #define OMAP3430_EN_GPT7 (1 << 8)
275 #define OMAP3430_EN_GPT7_SHIFT 8
276 #define OMAP3430_EN_GPT6 (1 << 7)
277 #define OMAP3430_EN_GPT6_SHIFT 7
278 #define OMAP3430_EN_GPT5 (1 << 6)
279 #define OMAP3430_EN_GPT5_SHIFT 6
280 #define OMAP3430_EN_GPT4 (1 << 5)
281 #define OMAP3430_EN_GPT4_SHIFT 5
282 #define OMAP3430_EN_GPT3 (1 << 4)
283 #define OMAP3430_EN_GPT3_SHIFT 4
284 #define OMAP3430_EN_GPT2 (1 << 3)
285 #define OMAP3430_EN_GPT2_SHIFT 3
287 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
288 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
289 * be ST_* bits instead? */
290 #define OMAP3430_EN_MCBSP4 (1 << 2)
291 #define OMAP3430_EN_MCBSP4_SHIFT 2
292 #define OMAP3430_EN_MCBSP3 (1 << 1)
293 #define OMAP3430_EN_MCBSP3_SHIFT 1
294 #define OMAP3430_EN_MCBSP2 (1 << 0)
295 #define OMAP3430_EN_MCBSP2_SHIFT 0
297 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
298 #define OMAP3430_ST_GPIO6 (1 << 17)
299 #define OMAP3430_ST_GPIO5 (1 << 16)
300 #define OMAP3430_ST_GPIO4 (1 << 15)
301 #define OMAP3430_ST_GPIO3 (1 << 14)
302 #define OMAP3430_ST_GPIO2 (1 << 13)
303 #define OMAP3430_ST_UART3 (1 << 11)
304 #define OMAP3430_ST_GPT9 (1 << 10)
305 #define OMAP3430_ST_GPT8 (1 << 9)
306 #define OMAP3430_ST_GPT7 (1 << 8)
307 #define OMAP3430_ST_GPT6 (1 << 7)
308 #define OMAP3430_ST_GPT5 (1 << 6)
309 #define OMAP3430_ST_GPT4 (1 << 5)
310 #define OMAP3430_ST_GPT3 (1 << 4)
311 #define OMAP3430_ST_GPT2 (1 << 3)
313 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
314 #define OMAP3430_EN_CORE (1 << 0)