2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static int omap1_clk_enable(struct clk * clk);
17 static void omap1_clk_disable(struct clk * clk);
18 static void omap1_ckctl_recalc(struct clk * clk);
19 static void omap1_watchdog_recalc(struct clk * clk);
20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
21 static int omap1_clk_enable_dsp_domain(struct clk * clk);
22 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
23 static void omap1_clk_disable_dsp_domain(struct clk * clk);
24 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
25 static void omap1_uart_recalc(struct clk * clk);
26 static int omap1_clk_enable_uart_functional(struct clk * clk);
27 static void omap1_clk_disable_uart_functional(struct clk * clk);
28 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
29 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
30 static void omap1_init_ext_clk(struct clk * clk);
31 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
32 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
33 static int omap1_clk_use(struct clk *clk);
34 static void omap1_clk_unuse(struct clk *clk);
39 unsigned long pll_rate;
46 unsigned long sysc_addr;
49 /* Provide a method for preventing idling some ARM IDLECT clocks */
50 struct arm_idlect1_clk {
52 unsigned long no_idle_count;
56 /* ARM_CKCTL bit shifts */
57 #define CKCTL_PERDIV_OFFSET 0
58 #define CKCTL_LCDDIV_OFFSET 2
59 #define CKCTL_ARMDIV_OFFSET 4
60 #define CKCTL_DSPDIV_OFFSET 6
61 #define CKCTL_TCDIV_OFFSET 8
62 #define CKCTL_DSPMMUDIV_OFFSET 10
63 /*#define ARM_TIMXO 12*/
65 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
66 /* DSP_CKCTL bit shifts */
67 #define CKCTL_DSPPERDIV_OFFSET 0
69 /* ARM_IDLECT2 bit shifts */
74 #define EN_LBCK 4 /* Not on 1610/1710 */
75 /*#define EN_HSABCK 5*/
79 #define EN_GPIOCK 9 /* Not on 1610/1710 */
80 /*#define EN_LBFREECK 10*/
81 #define EN_CKOUT_ARM 11
83 /* ARM_IDLECT3 bit shifts */
88 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
91 /* Various register defines for clock controls scattered around OMAP chip */
92 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
93 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
94 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
95 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
96 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
97 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
98 #define SOFT_REQ_REG 0xfffe0834
99 #define SOFT_REQ_REG2 0xfffe0880
101 /*-------------------------------------------------------------------------
102 * Omap1 MPU rate table
103 *-------------------------------------------------------------------------*/
104 static struct mpu_rate rate_table[] = {
105 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
106 * NOTE: Comment order here is different from bits in CKCTL value:
107 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
109 #if defined(CONFIG_OMAP_ARM_216MHZ)
110 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
112 #if defined(CONFIG_OMAP_ARM_195MHZ)
113 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
115 #if defined(CONFIG_OMAP_ARM_192MHZ)
116 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
117 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
118 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
119 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
120 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
122 #if defined(CONFIG_OMAP_ARM_182MHZ)
123 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
125 #if defined(CONFIG_OMAP_ARM_168MHZ)
126 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
128 #if defined(CONFIG_OMAP_ARM_150MHZ)
129 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
131 #if defined(CONFIG_OMAP_ARM_120MHZ)
132 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
134 #if defined(CONFIG_OMAP_ARM_96MHZ)
135 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
137 #if defined(CONFIG_OMAP_ARM_60MHZ)
138 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
140 #if defined(CONFIG_OMAP_ARM_30MHZ)
141 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
146 /*-------------------------------------------------------------------------
148 *-------------------------------------------------------------------------*/
150 static struct clk ck_ref = {
153 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
155 .enable = &omap1_clk_enable,
156 .disable = &omap1_clk_disable,
159 static struct clk ck_dpll1 = {
162 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
163 RATE_PROPAGATES | ALWAYS_ENABLED,
164 .enable = &omap1_clk_enable,
165 .disable = &omap1_clk_disable,
168 static struct arm_idlect1_clk ck_dpll1out = {
170 .name = "ck_dpll1out",
172 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,
173 .enable_reg = (void __iomem *)ARM_IDLECT2,
174 .enable_bit = EN_CKOUT_ARM,
175 .recalc = &followparent_recalc,
176 .enable = &omap1_clk_enable,
177 .disable = &omap1_clk_disable,
182 static struct clk arm_ck = {
185 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
186 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
187 .rate_offset = CKCTL_ARMDIV_OFFSET,
188 .recalc = &omap1_ckctl_recalc,
189 .enable = &omap1_clk_enable,
190 .disable = &omap1_clk_disable,
193 static struct arm_idlect1_clk armper_ck = {
197 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
198 RATE_CKCTL | CLOCK_IDLE_CONTROL,
199 .enable_reg = (void __iomem *)ARM_IDLECT2,
200 .enable_bit = EN_PERCK,
201 .rate_offset = CKCTL_PERDIV_OFFSET,
202 .recalc = &omap1_ckctl_recalc,
203 .enable = &omap1_clk_enable,
204 .disable = &omap1_clk_disable,
209 static struct clk arm_gpio_ck = {
210 .name = "arm_gpio_ck",
212 .flags = CLOCK_IN_OMAP1510,
213 .enable_reg = (void __iomem *)ARM_IDLECT2,
214 .enable_bit = EN_GPIOCK,
215 .recalc = &followparent_recalc,
216 .enable = &omap1_clk_enable,
217 .disable = &omap1_clk_disable,
220 static struct arm_idlect1_clk armxor_ck = {
224 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
226 .enable_reg = (void __iomem *)ARM_IDLECT2,
227 .enable_bit = EN_XORPCK,
228 .recalc = &followparent_recalc,
229 .enable = &omap1_clk_enable,
230 .disable = &omap1_clk_disable,
235 static struct arm_idlect1_clk armtim_ck = {
239 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
241 .enable_reg = (void __iomem *)ARM_IDLECT2,
242 .enable_bit = EN_TIMCK,
243 .recalc = &followparent_recalc,
244 .enable = &omap1_clk_enable,
245 .disable = &omap1_clk_disable,
250 static struct arm_idlect1_clk armwdt_ck = {
254 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
256 .enable_reg = (void __iomem *)ARM_IDLECT2,
257 .enable_bit = EN_WDTCK,
258 .recalc = &omap1_watchdog_recalc,
259 .enable = &omap1_clk_enable,
260 .disable = &omap1_clk_disable,
265 static struct clk arminth_ck16xx = {
266 .name = "arminth_ck",
268 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
269 .recalc = &followparent_recalc,
270 /* Note: On 16xx the frequency can be divided by 2 by programming
271 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
273 * 1510 version is in TC clocks.
275 .enable = &omap1_clk_enable,
276 .disable = &omap1_clk_disable,
279 static struct clk dsp_ck = {
282 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
284 .enable_reg = (void __iomem *)ARM_CKCTL,
285 .enable_bit = EN_DSPCK,
286 .rate_offset = CKCTL_DSPDIV_OFFSET,
287 .recalc = &omap1_ckctl_recalc,
288 .enable = &omap1_clk_enable,
289 .disable = &omap1_clk_disable,
292 static struct clk dspmmu_ck = {
295 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
296 RATE_CKCTL | ALWAYS_ENABLED,
297 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
298 .recalc = &omap1_ckctl_recalc,
299 .enable = &omap1_clk_enable,
300 .disable = &omap1_clk_disable,
303 static struct clk dspper_ck = {
306 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
307 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
308 .enable_reg = (void __iomem *)DSP_IDLECT2,
309 .enable_bit = EN_PERCK,
310 .rate_offset = CKCTL_PERDIV_OFFSET,
311 .recalc = &omap1_ckctl_recalc_dsp_domain,
312 .set_rate = &omap1_clk_set_rate_dsp_domain,
313 .enable = &omap1_clk_enable_dsp_domain,
314 .disable = &omap1_clk_disable_dsp_domain,
317 static struct clk dspxor_ck = {
320 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
322 .enable_reg = (void __iomem *)DSP_IDLECT2,
323 .enable_bit = EN_XORPCK,
324 .recalc = &followparent_recalc,
325 .enable = &omap1_clk_enable_dsp_domain,
326 .disable = &omap1_clk_disable_dsp_domain,
329 static struct clk dsptim_ck = {
332 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
334 .enable_reg = (void __iomem *)DSP_IDLECT2,
335 .enable_bit = EN_DSPTIMCK,
336 .recalc = &followparent_recalc,
337 .enable = &omap1_clk_enable_dsp_domain,
338 .disable = &omap1_clk_disable_dsp_domain,
341 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
342 static struct arm_idlect1_clk tc_ck = {
346 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
347 CLOCK_IN_OMAP730 | RATE_CKCTL |
348 RATE_PROPAGATES | ALWAYS_ENABLED |
350 .rate_offset = CKCTL_TCDIV_OFFSET,
351 .recalc = &omap1_ckctl_recalc,
352 .enable = &omap1_clk_enable,
353 .disable = &omap1_clk_disable,
358 static struct clk arminth_ck1510 = {
359 .name = "arminth_ck",
360 .parent = &tc_ck.clk,
361 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
362 .recalc = &followparent_recalc,
363 /* Note: On 1510 the frequency follows TC_CK
365 * 16xx version is in MPU clocks.
367 .enable = &omap1_clk_enable,
368 .disable = &omap1_clk_disable,
371 static struct clk tipb_ck = {
372 /* No-idle controlled by "tc_ck" */
374 .parent = &tc_ck.clk,
375 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
376 .recalc = &followparent_recalc,
377 .enable = &omap1_clk_enable,
378 .disable = &omap1_clk_disable,
381 static struct clk l3_ocpi_ck = {
382 /* No-idle controlled by "tc_ck" */
383 .name = "l3_ocpi_ck",
384 .parent = &tc_ck.clk,
385 .flags = CLOCK_IN_OMAP16XX,
386 .enable_reg = (void __iomem *)ARM_IDLECT3,
387 .enable_bit = EN_OCPI_CK,
388 .recalc = &followparent_recalc,
389 .enable = &omap1_clk_enable,
390 .disable = &omap1_clk_disable,
393 static struct clk tc1_ck = {
395 .parent = &tc_ck.clk,
396 .flags = CLOCK_IN_OMAP16XX,
397 .enable_reg = (void __iomem *)ARM_IDLECT3,
398 .enable_bit = EN_TC1_CK,
399 .recalc = &followparent_recalc,
400 .enable = &omap1_clk_enable,
401 .disable = &omap1_clk_disable,
404 static struct clk tc2_ck = {
406 .parent = &tc_ck.clk,
407 .flags = CLOCK_IN_OMAP16XX,
408 .enable_reg = (void __iomem *)ARM_IDLECT3,
409 .enable_bit = EN_TC2_CK,
410 .recalc = &followparent_recalc,
411 .enable = &omap1_clk_enable,
412 .disable = &omap1_clk_disable,
415 static struct clk dma_ck = {
416 /* No-idle controlled by "tc_ck" */
418 .parent = &tc_ck.clk,
419 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
421 .recalc = &followparent_recalc,
422 .enable = &omap1_clk_enable,
423 .disable = &omap1_clk_disable,
426 static struct clk dma_lcdfree_ck = {
427 .name = "dma_lcdfree_ck",
428 .parent = &tc_ck.clk,
429 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
430 .recalc = &followparent_recalc,
431 .enable = &omap1_clk_enable,
432 .disable = &omap1_clk_disable,
435 static struct arm_idlect1_clk api_ck = {
438 .parent = &tc_ck.clk,
439 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
441 .enable_reg = (void __iomem *)ARM_IDLECT2,
442 .enable_bit = EN_APICK,
443 .recalc = &followparent_recalc,
444 .enable = &omap1_clk_enable,
445 .disable = &omap1_clk_disable,
450 static struct arm_idlect1_clk lb_ck = {
453 .parent = &tc_ck.clk,
454 .flags = CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL,
455 .enable_reg = (void __iomem *)ARM_IDLECT2,
456 .enable_bit = EN_LBCK,
457 .recalc = &followparent_recalc,
458 .enable = &omap1_clk_enable,
459 .disable = &omap1_clk_disable,
464 static struct clk rhea1_ck = {
466 .parent = &tc_ck.clk,
467 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
468 .recalc = &followparent_recalc,
469 .enable = &omap1_clk_enable,
470 .disable = &omap1_clk_disable,
473 static struct clk rhea2_ck = {
475 .parent = &tc_ck.clk,
476 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
477 .recalc = &followparent_recalc,
478 .enable = &omap1_clk_enable,
479 .disable = &omap1_clk_disable,
482 static struct clk lcd_ck_16xx = {
485 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
486 .enable_reg = (void __iomem *)ARM_IDLECT2,
487 .enable_bit = EN_LCDCK,
488 .rate_offset = CKCTL_LCDDIV_OFFSET,
489 .recalc = &omap1_ckctl_recalc,
490 .enable = &omap1_clk_enable,
491 .disable = &omap1_clk_disable,
494 static struct arm_idlect1_clk lcd_ck_1510 = {
498 .flags = CLOCK_IN_OMAP1510 | RATE_CKCTL |
500 .enable_reg = (void __iomem *)ARM_IDLECT2,
501 .enable_bit = EN_LCDCK,
502 .rate_offset = CKCTL_LCDDIV_OFFSET,
503 .recalc = &omap1_ckctl_recalc,
504 .enable = &omap1_clk_enable,
505 .disable = &omap1_clk_disable,
510 static struct clk uart1_1510 = {
512 /* Direct from ULPD, no real parent */
513 .parent = &armper_ck.clk,
515 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
516 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
517 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
518 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
519 .set_rate = &omap1_set_uart_rate,
520 .recalc = &omap1_uart_recalc,
521 .enable = &omap1_clk_enable,
522 .disable = &omap1_clk_disable,
525 static struct uart_clk uart1_16xx = {
528 /* Direct from ULPD, no real parent */
529 .parent = &armper_ck.clk,
531 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
532 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
533 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
535 .enable = &omap1_clk_enable_uart_functional,
536 .disable = &omap1_clk_disable_uart_functional,
538 .sysc_addr = 0xfffb0054,
541 static struct clk uart2_ck = {
543 /* Direct from ULPD, no real parent */
544 .parent = &armper_ck.clk,
546 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
547 ENABLE_REG_32BIT | ALWAYS_ENABLED |
548 CLOCK_NO_IDLE_PARENT,
549 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
550 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
551 .set_rate = &omap1_set_uart_rate,
552 .recalc = &omap1_uart_recalc,
553 .enable = &omap1_clk_enable,
554 .disable = &omap1_clk_disable,
557 static struct clk uart3_1510 = {
559 /* Direct from ULPD, no real parent */
560 .parent = &armper_ck.clk,
562 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |
563 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
564 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
565 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
566 .set_rate = &omap1_set_uart_rate,
567 .recalc = &omap1_uart_recalc,
568 .enable = &omap1_clk_enable,
569 .disable = &omap1_clk_disable,
572 static struct uart_clk uart3_16xx = {
575 /* Direct from ULPD, no real parent */
576 .parent = &armper_ck.clk,
578 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
579 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
580 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
582 .enable = &omap1_clk_enable_uart_functional,
583 .disable = &omap1_clk_disable_uart_functional,
585 .sysc_addr = 0xfffb9854,
588 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
590 /* Direct from ULPD, no parent */
592 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
593 RATE_FIXED | ENABLE_REG_32BIT,
594 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
595 .enable_bit = USB_MCLK_EN_BIT,
596 .enable = &omap1_clk_enable,
597 .disable = &omap1_clk_disable,
600 static struct clk usb_hhc_ck1510 = {
601 .name = "usb_hhc_ck",
602 /* Direct from ULPD, no parent */
603 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
604 .flags = CLOCK_IN_OMAP1510 |
605 RATE_FIXED | ENABLE_REG_32BIT,
606 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
607 .enable_bit = USB_HOST_HHC_UHOST_EN,
608 .enable = &omap1_clk_enable,
609 .disable = &omap1_clk_disable,
612 static struct clk usb_hhc_ck16xx = {
613 .name = "usb_hhc_ck",
614 /* Direct from ULPD, no parent */
616 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
617 .flags = CLOCK_IN_OMAP16XX |
618 RATE_FIXED | ENABLE_REG_32BIT,
619 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
620 .enable_bit = 8 /* UHOST_EN */,
621 .enable = &omap1_clk_enable,
622 .disable = &omap1_clk_disable,
625 static struct clk usb_dc_ck = {
627 /* Direct from ULPD, no parent */
629 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
630 .enable_reg = (void __iomem *)SOFT_REQ_REG,
632 .enable = &omap1_clk_enable,
633 .disable = &omap1_clk_disable,
636 static struct clk mclk_1510 = {
638 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
640 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
641 .enable = &omap1_clk_enable,
642 .disable = &omap1_clk_disable,
645 static struct clk mclk_16xx = {
647 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
648 .flags = CLOCK_IN_OMAP16XX,
649 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
650 .enable_bit = COM_ULPD_PLL_CLK_REQ,
651 .set_rate = &omap1_set_ext_clk_rate,
652 .round_rate = &omap1_round_ext_clk_rate,
653 .init = &omap1_init_ext_clk,
654 .enable = &omap1_clk_enable,
655 .disable = &omap1_clk_disable,
658 static struct clk bclk_1510 = {
660 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
662 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
663 .enable = &omap1_clk_enable,
664 .disable = &omap1_clk_disable,
667 static struct clk bclk_16xx = {
669 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
670 .flags = CLOCK_IN_OMAP16XX,
671 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
672 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
673 .set_rate = &omap1_set_ext_clk_rate,
674 .round_rate = &omap1_round_ext_clk_rate,
675 .init = &omap1_init_ext_clk,
676 .enable = &omap1_clk_enable,
677 .disable = &omap1_clk_disable,
680 static struct clk mmc1_ck = {
682 /* Functional clock is direct from ULPD, interface clock is ARMPER */
683 .parent = &armper_ck.clk,
685 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
686 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
687 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
689 .enable = &omap1_clk_enable,
690 .disable = &omap1_clk_disable,
693 static struct clk mmc2_ck = {
695 /* Functional clock is direct from ULPD, interface clock is ARMPER */
696 .parent = &armper_ck.clk,
698 .flags = CLOCK_IN_OMAP16XX |
699 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
700 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
702 .enable = &omap1_clk_enable,
703 .disable = &omap1_clk_disable,
706 static struct clk virtual_ck_mpu = {
708 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
709 VIRTUAL_CLOCK | ALWAYS_ENABLED,
710 .parent = &arm_ck, /* Is smarter alias for */
711 .recalc = &followparent_recalc,
712 .set_rate = &omap1_select_table_rate,
713 .round_rate = &omap1_round_to_table_rate,
714 .enable = &omap1_clk_enable,
715 .disable = &omap1_clk_disable,
718 static struct clk * onchip_clks[] = {
719 /* non-ULPD clocks */
730 &arminth_ck1510, &arminth_ck16xx,
758 &usb_hhc_ck1510, &usb_hhc_ck16xx,
760 &mclk_1510, &mclk_16xx,
761 &bclk_1510, &bclk_16xx,