2 * linux/arch/arm/mach-at91rm9200/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
21 #include <asm/hardware.h>
22 #include <asm/arch/gpio.h>
27 static struct at91_gpio_bank *gpio;
28 static int gpio_banks;
31 static inline void __iomem *pin_to_controller(unsigned pin)
33 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
37 if (likely(pin < gpio_banks))
38 return sys_base + gpio[pin].offset;
43 static inline unsigned pin_to_mask(unsigned pin)
46 return 1 << (pin % 32);
50 /*--------------------------------------------------------------------------*/
52 /* Not all hardware capabilities are exposed through these calls; they
53 * only encapsulate the most common features and modes. (So if you
54 * want to change signals in groups, do it directly.)
56 * Bootloaders will usually handle some of the pin multiplexing setup.
57 * The intent is certainly that by the time Linux is fully booted, all
58 * pins should have been fully initialized. These setup calls should
59 * only be used by board setup routines, or possibly in driver probe().
61 * For bootloaders doing all that setup, these calls could be inlined
62 * as NOPs so Linux won't duplicate any setup code
67 * mux the pin to the "A" internal peripheral role.
69 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
71 void __iomem *pio = pin_to_controller(pin);
72 unsigned mask = pin_to_mask(pin);
77 __raw_writel(mask, pio + PIO_IDR);
78 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
79 __raw_writel(mask, pio + PIO_ASR);
80 __raw_writel(mask, pio + PIO_PDR);
83 EXPORT_SYMBOL(at91_set_A_periph);
87 * mux the pin to the "B" internal peripheral role.
89 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
91 void __iomem *pio = pin_to_controller(pin);
92 unsigned mask = pin_to_mask(pin);
97 __raw_writel(mask, pio + PIO_IDR);
98 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
99 __raw_writel(mask, pio + PIO_BSR);
100 __raw_writel(mask, pio + PIO_PDR);
103 EXPORT_SYMBOL(at91_set_B_periph);
107 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
108 * configure it for an input.
110 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
112 void __iomem *pio = pin_to_controller(pin);
113 unsigned mask = pin_to_mask(pin);
118 __raw_writel(mask, pio + PIO_IDR);
119 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
120 __raw_writel(mask, pio + PIO_ODR);
121 __raw_writel(mask, pio + PIO_PER);
124 EXPORT_SYMBOL(at91_set_gpio_input);
128 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
129 * and configure it for an output.
131 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
133 void __iomem *pio = pin_to_controller(pin);
134 unsigned mask = pin_to_mask(pin);
139 __raw_writel(mask, pio + PIO_IDR);
140 __raw_writel(mask, pio + PIO_PUDR);
141 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
142 __raw_writel(mask, pio + PIO_OER);
143 __raw_writel(mask, pio + PIO_PER);
146 EXPORT_SYMBOL(at91_set_gpio_output);
150 * enable/disable the glitch filter; mostly used with IRQ handling.
152 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
154 void __iomem *pio = pin_to_controller(pin);
155 unsigned mask = pin_to_mask(pin);
159 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
162 EXPORT_SYMBOL(at91_set_deglitch);
165 * enable/disable the multi-driver; This is only valid for output and
166 * allows the output pin to run as an open collector output.
168 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
170 void __iomem *pio = pin_to_controller(pin);
171 unsigned mask = pin_to_mask(pin);
176 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
179 EXPORT_SYMBOL(at91_set_multi_drive);
181 /*--------------------------------------------------------------------------*/
184 * assuming the pin is muxed as a gpio output, set its value.
186 int at91_set_gpio_value(unsigned pin, int value)
188 void __iomem *pio = pin_to_controller(pin);
189 unsigned mask = pin_to_mask(pin);
193 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
196 EXPORT_SYMBOL(at91_set_gpio_value);
200 * read the pin's value (works even if it's not muxed as a gpio).
202 int at91_get_gpio_value(unsigned pin)
204 void __iomem *pio = pin_to_controller(pin);
205 unsigned mask = pin_to_mask(pin);
210 pdsr = __raw_readl(pio + PIO_PDSR);
211 return (pdsr & mask) != 0;
213 EXPORT_SYMBOL(at91_get_gpio_value);
215 /*--------------------------------------------------------------------------*/
219 static u32 wakeups[MAX_GPIO_BANKS];
220 static u32 backups[MAX_GPIO_BANKS];
222 static int gpio_irq_set_wake(unsigned pin, unsigned state)
224 unsigned mask = pin_to_mask(pin);
229 if (unlikely(pin >= MAX_GPIO_BANKS))
233 wakeups[pin] |= mask;
235 wakeups[pin] &= ~mask;
240 void at91_gpio_suspend(void)
244 for (i = 0; i < gpio_banks; i++) {
245 u32 pio = gpio[i].offset;
248 * Note: drivers should have disabled GPIO interrupts that
249 * aren't supposed to be wakeup sources.
250 * But that is not much good on ARM..... disable_irq() does
251 * not update the hardware immediately, so the hardware mask
252 * (IMR) has the wrong value (not current, too much is
255 * Our workaround is to disable all non-wakeup IRQs ...
256 * which is exactly what correct drivers asked for in the
259 backups[i] = at91_sys_read(pio + PIO_IMR);
260 at91_sys_write(pio + PIO_IDR, backups[i]);
261 at91_sys_write(pio + PIO_IER, wakeups[i]);
264 disable_irq_wake(gpio[i].id);
265 at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
267 enable_irq_wake(gpio[i].id);
268 #ifdef CONFIG_PM_DEBUG
269 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
275 void at91_gpio_resume(void)
279 for (i = 0; i < gpio_banks; i++) {
280 u32 pio = gpio[i].offset;
282 at91_sys_write(pio + PIO_IDR, wakeups[i]);
283 at91_sys_write(pio + PIO_IER, backups[i]);
284 at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
289 #define gpio_irq_set_wake NULL
293 /* Several AIC controller irqs are dispatched through this GPIO handler.
294 * To use any AT91_PIN_* as an externally triggered IRQ, first call
295 * at91_set_gpio_input() then maybe enable its glitch filter.
296 * Then just request_irq() with the pin ID; it works like any ARM IRQ
297 * handler, though it always triggers on rising and falling edges.
299 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
300 * configuring them with at91_set_a_periph() or at91_set_b_periph().
301 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
304 static void gpio_irq_mask(unsigned pin)
306 void __iomem *pio = pin_to_controller(pin);
307 unsigned mask = pin_to_mask(pin);
310 __raw_writel(mask, pio + PIO_IDR);
313 static void gpio_irq_unmask(unsigned pin)
315 void __iomem *pio = pin_to_controller(pin);
316 unsigned mask = pin_to_mask(pin);
319 __raw_writel(mask, pio + PIO_IER);
322 static int gpio_irq_type(unsigned pin, unsigned type)
324 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
327 static struct irq_chip gpio_irqchip = {
329 .mask = gpio_irq_mask,
330 .unmask = gpio_irq_unmask,
331 .set_type = gpio_irq_type,
332 .set_wake = gpio_irq_set_wake,
335 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
338 struct irq_desc *gpio;
342 pio = get_irq_chip_data(irq);
344 /* temporarily mask (level sensitive) parent IRQ */
345 desc->chip->ack(irq);
347 /* reading ISR acks the pending (edge triggered) GPIO interrupt */
348 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
352 pin = (unsigned) get_irq_data(irq);
353 gpio = &irq_desc[pin];
357 if (unlikely(gpio->depth)) {
359 * The core ARM interrupt handler lazily disables IRQs so
360 * another IRQ must be generated before it actually gets
361 * here to be disabled on the GPIO controller.
366 desc_handle_irq(pin, gpio);
373 desc->chip->unmask(irq);
374 /* now it may re-trigger */
377 /*--------------------------------------------------------------------------*/
380 * Called from the processor-specific init to enable GPIO interrupt support.
382 void __init at91_gpio_irq_setup(void)
386 for (pioc = 0, pin = PIN_BASE;
389 void __iomem *controller;
390 unsigned id = gpio[pioc].id;
393 clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */
395 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
396 __raw_writel(~0, controller + PIO_IDR);
398 set_irq_data(id, (void *) pin);
399 set_irq_chip_data(id, controller);
401 for (i = 0; i < 32; i++, pin++) {
403 * Can use the "simple" and not "edge" handler since it's
404 * shorter, and the AIC handles interupts sanely.
406 set_irq_chip(pin, &gpio_irqchip);
407 set_irq_handler(pin, handle_simple_irq);
408 set_irq_flags(pin, IRQF_VALID);
411 set_irq_chained_handler(id, gpio_irq_handler);
413 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
417 * Called from the processor-specific init to enable GPIO pin support.
419 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
421 BUG_ON(nr_banks > MAX_GPIO_BANKS);
424 gpio_banks = nr_banks;