2 * linux/arch/arm/mach-at91rm9200/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
18 #include <asm/mach/irq.h>
19 #include <asm/hardware.h>
20 #include <asm/arch/gpio.h>
22 static const u32 pio_controller_offset[4] = {
29 static inline void __iomem *pin_to_controller(unsigned pin)
31 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
35 if (likely(pin < BGA_GPIO_BANKS))
36 return sys_base + pio_controller_offset[pin];
41 static inline unsigned pin_to_mask(unsigned pin)
44 return 1 << (pin % 32);
48 /*--------------------------------------------------------------------------*/
50 /* Not all hardware capabilities are exposed through these calls; they
51 * only encapsulate the most common features and modes. (So if you
52 * want to change signals in groups, do it directly.)
54 * Bootloaders will usually handle some of the pin multiplexing setup.
55 * The intent is certainly that by the time Linux is fully booted, all
56 * pins should have been fully initialized. These setup calls should
57 * only be used by board setup routines, or possibly in driver probe().
59 * For bootloaders doing all that setup, these calls could be inlined
60 * as NOPs so Linux won't duplicate any setup code
65 * mux the pin to the "A" internal peripheral role.
67 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
69 void __iomem *pio = pin_to_controller(pin);
70 unsigned mask = pin_to_mask(pin);
75 __raw_writel(mask, pio + PIO_IDR);
76 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
77 __raw_writel(mask, pio + PIO_ASR);
78 __raw_writel(mask, pio + PIO_PDR);
81 EXPORT_SYMBOL(at91_set_A_periph);
85 * mux the pin to the "B" internal peripheral role.
87 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
89 void __iomem *pio = pin_to_controller(pin);
90 unsigned mask = pin_to_mask(pin);
95 __raw_writel(mask, pio + PIO_IDR);
96 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
97 __raw_writel(mask, pio + PIO_BSR);
98 __raw_writel(mask, pio + PIO_PDR);
101 EXPORT_SYMBOL(at91_set_B_periph);
105 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
106 * configure it for an input.
108 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
110 void __iomem *pio = pin_to_controller(pin);
111 unsigned mask = pin_to_mask(pin);
116 __raw_writel(mask, pio + PIO_IDR);
117 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
118 __raw_writel(mask, pio + PIO_ODR);
119 __raw_writel(mask, pio + PIO_PER);
122 EXPORT_SYMBOL(at91_set_gpio_input);
126 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
127 * and configure it for an output.
129 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
131 void __iomem *pio = pin_to_controller(pin);
132 unsigned mask = pin_to_mask(pin);
137 __raw_writel(mask, pio + PIO_IDR);
138 __raw_writel(mask, pio + PIO_PUDR);
139 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
140 __raw_writel(mask, pio + PIO_OER);
141 __raw_writel(mask, pio + PIO_PER);
144 EXPORT_SYMBOL(at91_set_gpio_output);
148 * enable/disable the glitch filter; mostly used with IRQ handling.
150 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
152 void __iomem *pio = pin_to_controller(pin);
153 unsigned mask = pin_to_mask(pin);
157 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
160 EXPORT_SYMBOL(at91_set_deglitch);
163 * enable/disable the multi-driver; This is only valid for output and
164 * allows the output pin to run as an open collector output.
166 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
168 void __iomem *pio = pin_to_controller(pin);
169 unsigned mask = pin_to_mask(pin);
174 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
177 EXPORT_SYMBOL(at91_set_multi_drive);
179 /*--------------------------------------------------------------------------*/
183 * assuming the pin is muxed as a gpio output, set its value.
185 int at91_set_gpio_value(unsigned pin, int value)
187 void __iomem *pio = pin_to_controller(pin);
188 unsigned mask = pin_to_mask(pin);
192 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
195 EXPORT_SYMBOL(at91_set_gpio_value);
199 * read the pin's value (works even if it's not muxed as a gpio).
201 int at91_get_gpio_value(unsigned pin)
203 void __iomem *pio = pin_to_controller(pin);
204 unsigned mask = pin_to_mask(pin);
209 pdsr = __raw_readl(pio + PIO_PDSR);
210 return (pdsr & mask) != 0;
212 EXPORT_SYMBOL(at91_get_gpio_value);
214 /*--------------------------------------------------------------------------*/
218 static u32 wakeups[BGA_GPIO_BANKS];
219 static u32 backups[BGA_GPIO_BANKS];
221 static int gpio_irq_set_wake(unsigned pin, unsigned state)
223 unsigned mask = pin_to_mask(pin);
228 if (unlikely(pin >= BGA_GPIO_BANKS))
232 wakeups[pin] |= mask;
234 wakeups[pin] &= ~mask;
239 void at91_gpio_suspend(void)
243 for (i = 0; i < BGA_GPIO_BANKS; i++) {
244 u32 pio = pio_controller_offset[i];
247 * Note: drivers should have disabled GPIO interrupts that
248 * aren't supposed to be wakeup sources.
249 * But that is not much good on ARM..... disable_irq() does
250 * not update the hardware immediately, so the hardware mask
251 * (IMR) has the wrong value (not current, too much is
254 * Our workaround is to disable all non-wakeup IRQs ...
255 * which is exactly what correct drivers asked for in the
258 backups[i] = at91_sys_read(pio + PIO_IMR);
259 at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]);
260 at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]);
263 disable_irq_wake(AT91_ID_PIOA + i);
264 at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i));
266 enable_irq_wake(AT91_ID_PIOA + i);
267 #ifdef CONFIG_PM_DEBUG
268 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
274 void at91_gpio_resume(void)
278 for (i = 0; i < BGA_GPIO_BANKS; i++) {
279 at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]);
280 at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]);
283 at91_sys_write(AT91_PMC_PCER,
285 | (1 << AT91_ID_PIOB)
286 | (1 << AT91_ID_PIOC)
287 | (1 << AT91_ID_PIOD));
291 #define gpio_irq_set_wake NULL
295 /* Several AIC controller irqs are dispatched through this GPIO handler.
296 * To use any AT91_PIN_* as an externally triggered IRQ, first call
297 * at91_set_gpio_input() then maybe enable its glitch filter.
298 * Then just request_irq() with the pin ID; it works like any ARM IRQ
299 * handler, though it always triggers on rising and falling edges.
301 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
302 * configuring them with at91_set_a_periph() or at91_set_b_periph().
303 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
306 static void gpio_irq_mask(unsigned pin)
308 void __iomem *pio = pin_to_controller(pin);
309 unsigned mask = pin_to_mask(pin);
312 __raw_writel(mask, pio + PIO_IDR);
315 static void gpio_irq_unmask(unsigned pin)
317 void __iomem *pio = pin_to_controller(pin);
318 unsigned mask = pin_to_mask(pin);
321 __raw_writel(mask, pio + PIO_IER);
324 static int gpio_irq_type(unsigned pin, unsigned type)
326 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
329 static struct irqchip gpio_irqchip = {
330 .mask = gpio_irq_mask,
331 .unmask = gpio_irq_unmask,
332 .set_type = gpio_irq_type,
333 .set_wake = gpio_irq_set_wake,
336 static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
339 struct irqdesc *gpio;
345 /* temporarily mask (level sensitive) parent IRQ */
346 desc->chip->ack(irq);
348 /* reading ISR acks the pending (edge triggered) GPIO interrupt */
349 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
353 pin = (unsigned) desc->data;
354 gpio = &irq_desc[pin];
358 if (unlikely(gpio->disable_depth)) {
360 * The core ARM interrupt handler lazily disables IRQs so
361 * another IRQ must be generated before it actually gets
362 * here to be disabled on the GPIO controller.
367 gpio->handle(pin, gpio, regs);
374 desc->chip->unmask(irq);
375 /* now it may re-trigger */
378 /* call this from board-specific init_irq */
379 void __init at91_gpio_irq_setup(unsigned banks)
381 unsigned pioc, pin, id;
385 for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
388 void __iomem *controller;
391 controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
392 __raw_writel(~0, controller + PIO_IDR);
394 set_irq_data(id, (void *) pin);
395 set_irq_chipdata(id, controller);
397 for (i = 0; i < 32; i++, pin++) {
399 * Can use the "simple" and not "edge" handler since it's
400 * shorter, and the AIC handles interupts sanely.
402 set_irq_chip(pin, &gpio_irqchip);
403 set_irq_handler(pin, do_simple_IRQ);
404 set_irq_flags(pin, IRQF_VALID);
407 set_irq_chained_handler(id, gpio_irq_handler);
409 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);