2 * linux/arch/arm/mach-at91rm9200/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <asm/semaphore.h>
28 #include <asm/mach-types.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/board.h> /* for master clock global */
38 * There's a lot more which can be done with clocks, including cpufreq
39 * integration, slow clock mode support (for system suspend), letting
40 * PLLB be used at other rates (on boards that don't need USB), etc.
45 unsigned long rate_hz;
48 void (*mode)(struct clk *, int);
49 unsigned id:2; /* PCK0..3, or 32k/main/a/b */
52 unsigned programmable:1;
56 static spinlock_t clk_lock;
57 static u32 at91_pllb_usb_init;
60 * Four primary clock sources: two crystal oscillators (32K, main), and
61 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
62 * 48 MHz (unless no USB function clocks are needed). The main clock and
63 * both PLLs are turned off to run in "slow clock mode" (system suspend).
65 static struct clk clk32k = {
67 .rate_hz = AT91_SLOW_CLOCK,
68 .users = 1, /* always on */
72 static struct clk main_clk = {
74 .pmc_mask = 1 << 0, /* in PMC_SR */
79 static struct clk plla = {
82 .pmc_mask = 1 << 1, /* in PMC_SR */
88 static void pllb_mode(struct clk *clk, int is_on)
93 is_on = AT91_PMC_LOCKB;
94 value = at91_pllb_usb_init;
98 at91_sys_write(AT91_CKGR_PLLBR, value);
102 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
105 static struct clk pllb = {
108 .pmc_mask = 1 << 2, /* in PMC_SR */
115 static void pmc_sys_mode(struct clk *clk, int is_on)
118 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
120 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
123 /* USB function clocks (PLLB must be 48 MHz) */
124 static struct clk udpck = {
127 .pmc_mask = AT91_PMC_UDP,
128 .mode = pmc_sys_mode,
130 static struct clk uhpck = {
133 .pmc_mask = AT91_PMC_UHP,
134 .mode = pmc_sys_mode,
137 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
139 * The four programmable clocks can be parented by any primary clock.
140 * You must configure pin multiplexing to bring these signals out.
142 static struct clk pck0 = {
144 .pmc_mask = AT91_PMC_PCK0,
145 .mode = pmc_sys_mode,
149 static struct clk pck1 = {
151 .pmc_mask = AT91_PMC_PCK1,
152 .mode = pmc_sys_mode,
156 static struct clk pck2 = {
158 .pmc_mask = AT91_PMC_PCK2,
159 .mode = pmc_sys_mode,
163 static struct clk pck3 = {
165 .pmc_mask = AT91_PMC_PCK3,
166 .mode = pmc_sys_mode,
170 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
174 * The master clock is divided from the CPU clock (by 1-4). It's used for
175 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
176 * (e.g baud rate generation). It's sourced from one of the primary clocks.
178 static struct clk mck = {
180 .pmc_mask = 1 << 3, /* in PMC_SR */
181 .users = 1, /* (must be) always on */
184 static void pmc_periph_mode(struct clk *clk, int is_on)
187 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
189 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
192 static struct clk udc_clk = {
195 .pmc_mask = 1 << AT91_ID_UDP,
196 .mode = pmc_periph_mode,
198 static struct clk ohci_clk = {
201 .pmc_mask = 1 << AT91_ID_UHP,
202 .mode = pmc_periph_mode,
205 static struct clk *const clock_list[] = {
206 /* four primary clocks -- MUST BE FIRST! */
212 /* PLLB children (USB) */
216 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
217 /* programmable clocks */
222 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
224 /* MCK and peripherals */
238 /* clocks are all static for now; no refcounting necessary */
239 struct clk *clk_get(struct device *dev, const char *id)
243 for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
244 if (strcmp(id, clock_list[i]->name) == 0)
245 return clock_list[i];
248 return ERR_PTR(-ENOENT);
250 EXPORT_SYMBOL(clk_get);
252 void clk_put(struct clk *clk)
255 EXPORT_SYMBOL(clk_put);
257 static void __clk_enable(struct clk *clk)
260 __clk_enable(clk->parent);
261 if (clk->users++ == 0 && clk->mode)
265 int clk_enable(struct clk *clk)
269 spin_lock_irqsave(&clk_lock, flags);
271 spin_unlock_irqrestore(&clk_lock, flags);
274 EXPORT_SYMBOL(clk_enable);
276 static void __clk_disable(struct clk *clk)
278 BUG_ON(clk->users == 0);
279 if (--clk->users == 0 && clk->mode)
282 __clk_disable(clk->parent);
285 void clk_disable(struct clk *clk)
289 spin_lock_irqsave(&clk_lock, flags);
291 spin_unlock_irqrestore(&clk_lock, flags);
293 EXPORT_SYMBOL(clk_disable);
295 unsigned long clk_get_rate(struct clk *clk)
300 spin_lock_irqsave(&clk_lock, flags);
303 if (rate || !clk->parent)
307 spin_unlock_irqrestore(&clk_lock, flags);
310 EXPORT_SYMBOL(clk_get_rate);
312 /*------------------------------------------------------------------------*/
314 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
317 * For now, only the programmable clocks support reparenting (MCK could
318 * do this too, with care) or rate changing (the PLLs could do this too,
319 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
320 * a better rate match; we don't.
323 long clk_round_rate(struct clk *clk, unsigned long rate)
327 unsigned long actual;
329 if (!clk->programmable)
331 spin_lock_irqsave(&clk_lock, flags);
333 actual = clk->parent->rate_hz;
334 for (prescale = 0; prescale < 7; prescale++) {
335 if (actual && actual <= rate)
340 spin_unlock_irqrestore(&clk_lock, flags);
341 return (prescale < 7) ? actual : -ENOENT;
343 EXPORT_SYMBOL(clk_round_rate);
345 int clk_set_rate(struct clk *clk, unsigned long rate)
349 unsigned long actual;
351 if (!clk->programmable)
355 spin_lock_irqsave(&clk_lock, flags);
357 actual = clk->parent->rate_hz;
358 for (prescale = 0; prescale < 7; prescale++) {
359 if (actual && actual <= rate) {
362 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
364 pckr |= prescale << 2;
365 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
366 clk->rate_hz = actual;
372 spin_unlock_irqrestore(&clk_lock, flags);
373 return (prescale < 7) ? actual : -ENOENT;
375 EXPORT_SYMBOL(clk_set_rate);
377 struct clk *clk_get_parent(struct clk *clk)
381 EXPORT_SYMBOL(clk_get_parent);
383 int clk_set_parent(struct clk *clk, struct clk *parent)
389 if (!parent->primary || !clk->programmable)
391 spin_lock_irqsave(&clk_lock, flags);
393 clk->rate_hz = parent->rate_hz;
394 clk->parent = parent;
395 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
397 spin_unlock_irqrestore(&clk_lock, flags);
400 EXPORT_SYMBOL(clk_set_parent);
402 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
404 /*------------------------------------------------------------------------*/
406 #ifdef CONFIG_DEBUG_FS
408 static int at91_clk_show(struct seq_file *s, void *unused)
413 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
414 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
416 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
417 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
418 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
419 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
421 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
422 for (i = 0; i < 4; i++)
423 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
424 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
428 for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
430 struct clk *clk = clock_list[i];
432 if (clk->mode == pmc_sys_mode)
433 state = (scsr & clk->pmc_mask) ? "on" : "off";
434 else if (clk->mode == pmc_periph_mode)
435 state = (pcsr & clk->pmc_mask) ? "on" : "off";
436 else if (clk->pmc_mask)
437 state = (sr & clk->pmc_mask) ? "on" : "off";
438 else if (clk == &clk32k || clk == &main_clk)
443 seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n",
444 clk->name, clk->users, state, clk_get_rate(clk),
445 clk->parent ? clk->parent->name : "");
450 static int at91_clk_open(struct inode *inode, struct file *file)
452 return single_open(file, at91_clk_show, NULL);
455 static struct file_operations at91_clk_operations = {
456 .open = at91_clk_open,
459 .release = single_release,
462 static int __init at91_clk_debugfs_init(void)
464 /* /sys/kernel/debug/at91_clk */
465 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
469 postcore_initcall(at91_clk_debugfs_init);
473 /*------------------------------------------------------------------------*/
475 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
480 mul = (reg >> 16) & 0x7ff;
486 if (pll == &pllb && (reg & (1 << 28)))
491 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
493 unsigned i, div = 0, mul = 0, diff = 1 << 30;
494 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
496 /* PLL output max 240 MHz (or 180 MHz per errata) */
497 if (out_freq > 240000000)
500 for (i = 1; i < 256; i++) {
502 unsigned input, mul1;
505 * PLL input between 1MHz and 32MHz per spec, but lower
506 * frequences seem necessary in some cases so allow 100K.
508 input = main_freq / i;
511 if (input > 32000000)
514 mul1 = out_freq / input;
520 diff1 = out_freq - input * mul1;
531 if (i == 256 && diff > (out_freq >> 5))
533 return ret | ((mul - 1) << 16) | div;
538 int __init at91_clock_init(unsigned long main_clock)
540 unsigned tmp, freq, mckr;
542 spin_lock_init(&clk_lock);
545 * When the bootloader initialized the main oscillator correctly,
546 * there's no problem using the cycle counter. But if it didn't,
547 * or when using oscillator bypass mode, we must be told the speed
552 tmp = at91_sys_read(AT91_CKGR_MCFR);
553 } while (!(tmp & 0x10000));
554 main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16);
556 main_clk.rate_hz = main_clock;
558 /* report if PLLA is more than mildly overclocked */
559 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
560 if (plla.rate_hz > 209000000)
561 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
564 * USB clock init: choose 48 MHz PLLB value, turn all clocks off,
565 * disable 48MHz clock during usb peripheral suspend.
567 * REVISIT: assumes MCK doesn't derive from PLLB!
569 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000;
570 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
571 at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
572 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
573 at91_sys_write(AT91_CKGR_PLLBR, 0);
574 at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
577 * MCK and CPU derive from one of those primary clocks.
578 * For now, assume this parentage won't change.
580 mckr = at91_sys_read(AT91_PMC_MCKR);
581 mck.parent = clock_list[mckr & AT91_PMC_CSS];
583 freq = mck.parent->rate_hz;
584 freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
585 mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
587 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
588 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
589 (unsigned) main_clock / 1000000,
590 ((unsigned) main_clock % 1000000) / 1000);
592 /* FIXME get rid of master_clock global */
593 at91_master_clock = mck.rate_hz;
595 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
596 /* establish PCK0..PCK3 parentage */
597 for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
598 struct clk *clk = clock_list[tmp], *parent;
601 if (!clk->programmable)
604 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
605 parent = clock_list[pckr & 3];
606 clk->parent = parent;
607 clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
610 /* disable unused clocks */
611 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
612 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
614 /* FIXME several unused clocks may still be active... provide
615 * a CONFIG option to turn off all unused clocks at some point
616 * before driver init starts.