2 * arch/arm/mach-at91/at91rm9200_devices.c
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
20 #include <asm/arch/board.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/at91rm9200.h>
23 #include <asm/arch/at91rm9200_mc.h>
28 /* --------------------------------------------------------------------
30 * -------------------------------------------------------------------- */
32 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
33 static u64 ohci_dmamask = DMA_BIT_MASK(32);
34 static struct at91_usbh_data usbh_data;
36 static struct resource usbh_resources[] = {
38 .start = AT91RM9200_UHP_BASE,
39 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM,
43 .start = AT91RM9200_ID_UHP,
44 .end = AT91RM9200_ID_UHP,
45 .flags = IORESOURCE_IRQ,
49 static struct platform_device at91rm9200_usbh_device = {
53 .dma_mask = &ohci_dmamask,
54 .coherent_dma_mask = DMA_BIT_MASK(32),
55 .platform_data = &usbh_data,
57 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(usbh_resources),
61 void __init at91_add_device_usbh(struct at91_usbh_data *data)
67 platform_device_register(&at91rm9200_usbh_device);
70 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
74 /* --------------------------------------------------------------------
76 * -------------------------------------------------------------------- */
78 #ifdef CONFIG_USB_GADGET_AT91
79 static struct at91_udc_data udc_data;
81 static struct resource udc_resources[] = {
83 .start = AT91RM9200_BASE_UDP,
84 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM,
88 .start = AT91RM9200_ID_UDP,
89 .end = AT91RM9200_ID_UDP,
90 .flags = IORESOURCE_IRQ,
94 static struct platform_device at91rm9200_udc_device = {
98 .platform_data = &udc_data,
100 .resource = udc_resources,
101 .num_resources = ARRAY_SIZE(udc_resources),
104 void __init at91_add_device_udc(struct at91_udc_data *data)
109 if (data->vbus_pin) {
110 at91_set_gpio_input(data->vbus_pin, 0);
111 at91_set_deglitch(data->vbus_pin, 1);
113 if (data->pullup_pin)
114 at91_set_gpio_output(data->pullup_pin, 0);
117 platform_device_register(&at91rm9200_udc_device);
120 void __init at91_add_device_udc(struct at91_udc_data *data) {}
124 /* --------------------------------------------------------------------
126 * -------------------------------------------------------------------- */
128 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
129 static u64 eth_dmamask = DMA_BIT_MASK(32);
130 static struct at91_eth_data eth_data;
132 static struct resource eth_resources[] = {
134 .start = AT91_VA_BASE_EMAC,
135 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM,
139 .start = AT91RM9200_ID_EMAC,
140 .end = AT91RM9200_ID_EMAC,
141 .flags = IORESOURCE_IRQ,
145 static struct platform_device at91rm9200_eth_device = {
146 .name = "at91_ether",
149 .dma_mask = ð_dmamask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
151 .platform_data = ð_data,
153 .resource = eth_resources,
154 .num_resources = ARRAY_SIZE(eth_resources),
157 void __init at91_add_device_eth(struct at91_eth_data *data)
162 if (data->phy_irq_pin) {
163 at91_set_gpio_input(data->phy_irq_pin, 0);
164 at91_set_deglitch(data->phy_irq_pin, 1);
167 /* Pins used for MII and RMII */
168 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
169 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
171 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
172 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
173 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
174 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
175 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
176 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
177 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
179 if (!data->is_rmii) {
180 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
181 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
182 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
183 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
184 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
185 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
186 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
187 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
191 platform_device_register(&at91rm9200_eth_device);
194 void __init at91_add_device_eth(struct at91_eth_data *data) {}
198 /* --------------------------------------------------------------------
199 * Compact Flash / PCMCIA
200 * -------------------------------------------------------------------- */
202 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
203 static struct at91_cf_data cf_data;
205 #define CF_BASE AT91_CHIPSELECT_4
207 static struct resource cf_resources[] = {
210 /* ties up CS4, CS5 and CS6 */
211 .end = CF_BASE + (0x30000000 - 1),
212 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
216 static struct platform_device at91rm9200_cf_device = {
220 .platform_data = &cf_data,
222 .resource = cf_resources,
223 .num_resources = ARRAY_SIZE(cf_resources),
226 void __init at91_add_device_cf(struct at91_cf_data *data)
233 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
235 /* CF takes over CS4, CS5, CS6 */
236 csa = at91_sys_read(AT91_EBI_CSA);
237 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
240 * Static memory controller timing adjustments.
241 * REVISIT: these timings are in terms of MCK cycles, so
242 * when MCK changes (cpufreq etc) so must these values...
244 at91_sys_write(AT91_SMC_CSR(4),
249 | AT91_SMC_NWS_(32) /* wait states */
250 | AT91_SMC_RWSETUP_(6) /* setup time */
251 | AT91_SMC_RWHOLD_(4) /* hold time */
256 at91_set_gpio_input(data->irq_pin, 1);
257 at91_set_deglitch(data->irq_pin, 1);
259 at91_set_gpio_input(data->det_pin, 1);
260 at91_set_deglitch(data->det_pin, 1);
262 /* outputs, initially off */
264 at91_set_gpio_output(data->vcc_pin, 0);
265 at91_set_gpio_output(data->rst_pin, 0);
267 /* force poweron defaults for these pins ... */
268 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
269 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
270 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
271 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
273 /* nWAIT is _not_ a default setting */
274 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
277 platform_device_register(&at91rm9200_cf_device);
280 void __init at91_add_device_cf(struct at91_cf_data *data) {}
284 /* --------------------------------------------------------------------
286 * -------------------------------------------------------------------- */
288 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
289 static u64 mmc_dmamask = DMA_BIT_MASK(32);
290 static struct at91_mmc_data mmc_data;
292 static struct resource mmc_resources[] = {
294 .start = AT91RM9200_BASE_MCI,
295 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
296 .flags = IORESOURCE_MEM,
299 .start = AT91RM9200_ID_MCI,
300 .end = AT91RM9200_ID_MCI,
301 .flags = IORESOURCE_IRQ,
305 static struct platform_device at91rm9200_mmc_device = {
309 .dma_mask = &mmc_dmamask,
310 .coherent_dma_mask = DMA_BIT_MASK(32),
311 .platform_data = &mmc_data,
313 .resource = mmc_resources,
314 .num_resources = ARRAY_SIZE(mmc_resources),
317 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
324 at91_set_gpio_input(data->det_pin, 1);
325 at91_set_deglitch(data->det_pin, 1);
328 at91_set_gpio_input(data->wp_pin, 1);
330 at91_set_gpio_output(data->vcc_pin, 0);
333 at91_set_A_periph(AT91_PIN_PA27, 0);
337 at91_set_B_periph(AT91_PIN_PA8, 1);
339 /* DAT0, maybe DAT1..DAT3 */
340 at91_set_B_periph(AT91_PIN_PA9, 1);
342 at91_set_B_periph(AT91_PIN_PA10, 1);
343 at91_set_B_periph(AT91_PIN_PA11, 1);
344 at91_set_B_periph(AT91_PIN_PA12, 1);
348 at91_set_A_periph(AT91_PIN_PA28, 1);
350 /* DAT0, maybe DAT1..DAT3 */
351 at91_set_A_periph(AT91_PIN_PA29, 1);
353 at91_set_B_periph(AT91_PIN_PB3, 1);
354 at91_set_B_periph(AT91_PIN_PB4, 1);
355 at91_set_B_periph(AT91_PIN_PB5, 1);
360 platform_device_register(&at91rm9200_mmc_device);
363 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
367 /* --------------------------------------------------------------------
369 * -------------------------------------------------------------------- */
371 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
372 static struct at91_nand_data nand_data;
374 #define NAND_BASE AT91_CHIPSELECT_3
376 static struct resource nand_resources[] = {
379 .end = NAND_BASE + SZ_256M - 1,
380 .flags = IORESOURCE_MEM,
384 static struct platform_device at91rm9200_nand_device = {
388 .platform_data = &nand_data,
390 .resource = nand_resources,
391 .num_resources = ARRAY_SIZE(nand_resources),
394 void __init at91_add_device_nand(struct at91_nand_data *data)
401 /* enable the address range of CS3 */
402 csa = at91_sys_read(AT91_EBI_CSA);
403 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
405 /* set the bus interface characteristics */
406 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
409 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
410 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
414 if (data->enable_pin)
415 at91_set_gpio_output(data->enable_pin, 1);
419 at91_set_gpio_input(data->rdy_pin, 1);
421 /* card detect pin */
423 at91_set_gpio_input(data->det_pin, 1);
425 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
426 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
429 platform_device_register(&at91rm9200_nand_device);
432 void __init at91_add_device_nand(struct at91_nand_data *data) {}
436 /* --------------------------------------------------------------------
438 * -------------------------------------------------------------------- */
441 * Prefer the GPIO code since the TWI controller isn't robust
442 * (gets overruns and underruns under load) and can only issue
443 * repeated STARTs in one scenario (the driver doesn't yet handle them).
445 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
447 static struct i2c_gpio_platform_data pdata = {
448 .sda_pin = AT91_PIN_PA25,
449 .sda_is_open_drain = 1,
450 .scl_pin = AT91_PIN_PA26,
451 .scl_is_open_drain = 1,
452 .udelay = 2, /* ~100 kHz */
455 static struct platform_device at91rm9200_twi_device = {
458 .dev.platform_data = &pdata,
461 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
463 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
464 at91_set_multi_drive(AT91_PIN_PA25, 1);
466 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
467 at91_set_multi_drive(AT91_PIN_PA26, 1);
469 i2c_register_board_info(0, devices, nr_devices);
470 platform_device_register(&at91rm9200_twi_device);
473 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
475 static struct resource twi_resources[] = {
477 .start = AT91RM9200_BASE_TWI,
478 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
479 .flags = IORESOURCE_MEM,
482 .start = AT91RM9200_ID_TWI,
483 .end = AT91RM9200_ID_TWI,
484 .flags = IORESOURCE_IRQ,
488 static struct platform_device at91rm9200_twi_device = {
491 .resource = twi_resources,
492 .num_resources = ARRAY_SIZE(twi_resources),
495 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
497 /* pins used for TWI interface */
498 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
499 at91_set_multi_drive(AT91_PIN_PA25, 1);
501 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
502 at91_set_multi_drive(AT91_PIN_PA26, 1);
504 i2c_register_board_info(0, devices, nr_devices);
505 platform_device_register(&at91rm9200_twi_device);
508 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
512 /* --------------------------------------------------------------------
514 * -------------------------------------------------------------------- */
516 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
517 static u64 spi_dmamask = DMA_BIT_MASK(32);
519 static struct resource spi_resources[] = {
521 .start = AT91RM9200_BASE_SPI,
522 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
523 .flags = IORESOURCE_MEM,
526 .start = AT91RM9200_ID_SPI,
527 .end = AT91RM9200_ID_SPI,
528 .flags = IORESOURCE_IRQ,
532 static struct platform_device at91rm9200_spi_device = {
536 .dma_mask = &spi_dmamask,
537 .coherent_dma_mask = DMA_BIT_MASK(32),
539 .resource = spi_resources,
540 .num_resources = ARRAY_SIZE(spi_resources),
543 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
545 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
548 unsigned long cs_pin;
550 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
551 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
552 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
554 /* Enable SPI chip-selects */
555 for (i = 0; i < nr_devices; i++) {
556 if (devices[i].controller_data)
557 cs_pin = (unsigned long) devices[i].controller_data;
559 cs_pin = spi_standard_cs[devices[i].chip_select];
561 /* enable chip-select pin */
562 at91_set_gpio_output(cs_pin, 1);
564 /* pass chip-select pin to driver */
565 devices[i].controller_data = (void *) cs_pin;
568 spi_register_board_info(devices, nr_devices);
569 platform_device_register(&at91rm9200_spi_device);
572 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
576 /* --------------------------------------------------------------------
578 * -------------------------------------------------------------------- */
580 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
581 static struct platform_device at91rm9200_rtc_device = {
587 static void __init at91_add_device_rtc(void)
589 platform_device_register(&at91rm9200_rtc_device);
592 static void __init at91_add_device_rtc(void) {}
596 /* --------------------------------------------------------------------
598 * -------------------------------------------------------------------- */
600 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
601 static struct platform_device at91rm9200_wdt_device = {
607 static void __init at91_add_device_watchdog(void)
609 platform_device_register(&at91rm9200_wdt_device);
612 static void __init at91_add_device_watchdog(void) {}
616 /* --------------------------------------------------------------------
617 * SSC -- Synchronous Serial Controller
618 * -------------------------------------------------------------------- */
620 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
621 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
623 static struct resource ssc0_resources[] = {
625 .start = AT91RM9200_BASE_SSC0,
626 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
627 .flags = IORESOURCE_MEM,
630 .start = AT91RM9200_ID_SSC0,
631 .end = AT91RM9200_ID_SSC0,
632 .flags = IORESOURCE_IRQ,
636 static struct platform_device at91rm9200_ssc0_device = {
640 .dma_mask = &ssc0_dmamask,
641 .coherent_dma_mask = DMA_BIT_MASK(32),
643 .resource = ssc0_resources,
644 .num_resources = ARRAY_SIZE(ssc0_resources),
647 static inline void configure_ssc0_pins(unsigned pins)
649 if (pins & ATMEL_SSC_TF)
650 at91_set_A_periph(AT91_PIN_PB0, 1);
651 if (pins & ATMEL_SSC_TK)
652 at91_set_A_periph(AT91_PIN_PB1, 1);
653 if (pins & ATMEL_SSC_TD)
654 at91_set_A_periph(AT91_PIN_PB2, 1);
655 if (pins & ATMEL_SSC_RD)
656 at91_set_A_periph(AT91_PIN_PB3, 1);
657 if (pins & ATMEL_SSC_RK)
658 at91_set_A_periph(AT91_PIN_PB4, 1);
659 if (pins & ATMEL_SSC_RF)
660 at91_set_A_periph(AT91_PIN_PB5, 1);
663 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
665 static struct resource ssc1_resources[] = {
667 .start = AT91RM9200_BASE_SSC1,
668 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
669 .flags = IORESOURCE_MEM,
672 .start = AT91RM9200_ID_SSC1,
673 .end = AT91RM9200_ID_SSC1,
674 .flags = IORESOURCE_IRQ,
678 static struct platform_device at91rm9200_ssc1_device = {
682 .dma_mask = &ssc1_dmamask,
683 .coherent_dma_mask = DMA_BIT_MASK(32),
685 .resource = ssc1_resources,
686 .num_resources = ARRAY_SIZE(ssc1_resources),
689 static inline void configure_ssc1_pins(unsigned pins)
691 if (pins & ATMEL_SSC_TF)
692 at91_set_A_periph(AT91_PIN_PB6, 1);
693 if (pins & ATMEL_SSC_TK)
694 at91_set_A_periph(AT91_PIN_PB7, 1);
695 if (pins & ATMEL_SSC_TD)
696 at91_set_A_periph(AT91_PIN_PB8, 1);
697 if (pins & ATMEL_SSC_RD)
698 at91_set_A_periph(AT91_PIN_PB9, 1);
699 if (pins & ATMEL_SSC_RK)
700 at91_set_A_periph(AT91_PIN_PB10, 1);
701 if (pins & ATMEL_SSC_RF)
702 at91_set_A_periph(AT91_PIN_PB11, 1);
705 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
707 static struct resource ssc2_resources[] = {
709 .start = AT91RM9200_BASE_SSC2,
710 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
711 .flags = IORESOURCE_MEM,
714 .start = AT91RM9200_ID_SSC2,
715 .end = AT91RM9200_ID_SSC2,
716 .flags = IORESOURCE_IRQ,
720 static struct platform_device at91rm9200_ssc2_device = {
724 .dma_mask = &ssc2_dmamask,
725 .coherent_dma_mask = DMA_BIT_MASK(32),
727 .resource = ssc2_resources,
728 .num_resources = ARRAY_SIZE(ssc2_resources),
731 static inline void configure_ssc2_pins(unsigned pins)
733 if (pins & ATMEL_SSC_TF)
734 at91_set_A_periph(AT91_PIN_PB12, 1);
735 if (pins & ATMEL_SSC_TK)
736 at91_set_A_periph(AT91_PIN_PB13, 1);
737 if (pins & ATMEL_SSC_TD)
738 at91_set_A_periph(AT91_PIN_PB14, 1);
739 if (pins & ATMEL_SSC_RD)
740 at91_set_A_periph(AT91_PIN_PB15, 1);
741 if (pins & ATMEL_SSC_RK)
742 at91_set_A_periph(AT91_PIN_PB16, 1);
743 if (pins & ATMEL_SSC_RF)
744 at91_set_A_periph(AT91_PIN_PB17, 1);
748 * SSC controllers are accessed through library code, instead of any
749 * kind of all-singing/all-dancing driver. For example one could be
750 * used by a particular I2S audio codec's driver, while another one
751 * on the same system might be used by a custom data capture driver.
753 void __init at91_add_device_ssc(unsigned id, unsigned pins)
755 struct platform_device *pdev;
758 * NOTE: caller is responsible for passing information matching
759 * "pins" to whatever will be using each particular controller.
762 case AT91RM9200_ID_SSC0:
763 pdev = &at91rm9200_ssc0_device;
764 configure_ssc0_pins(pins);
765 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
767 case AT91RM9200_ID_SSC1:
768 pdev = &at91rm9200_ssc1_device;
769 configure_ssc1_pins(pins);
770 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
772 case AT91RM9200_ID_SSC2:
773 pdev = &at91rm9200_ssc2_device;
774 configure_ssc2_pins(pins);
775 at91_clock_associate("ssc2_clk", &pdev->dev, "ssc");
781 platform_device_register(pdev);
785 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
789 /* --------------------------------------------------------------------
791 * -------------------------------------------------------------------- */
793 #if defined(CONFIG_SERIAL_ATMEL)
794 static struct resource dbgu_resources[] = {
796 .start = AT91_VA_BASE_SYS + AT91_DBGU,
797 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
798 .flags = IORESOURCE_MEM,
801 .start = AT91_ID_SYS,
803 .flags = IORESOURCE_IRQ,
807 static struct atmel_uart_data dbgu_data = {
809 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
810 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
813 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
815 static struct platform_device at91rm9200_dbgu_device = {
816 .name = "atmel_usart",
819 .dma_mask = &dbgu_dmamask,
820 .coherent_dma_mask = DMA_BIT_MASK(32),
821 .platform_data = &dbgu_data,
823 .resource = dbgu_resources,
824 .num_resources = ARRAY_SIZE(dbgu_resources),
827 static inline void configure_dbgu_pins(void)
829 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
830 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
833 static struct resource uart0_resources[] = {
835 .start = AT91RM9200_BASE_US0,
836 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
837 .flags = IORESOURCE_MEM,
840 .start = AT91RM9200_ID_US0,
841 .end = AT91RM9200_ID_US0,
842 .flags = IORESOURCE_IRQ,
846 static struct atmel_uart_data uart0_data = {
851 static u64 uart0_dmamask = DMA_BIT_MASK(32);
853 static struct platform_device at91rm9200_uart0_device = {
854 .name = "atmel_usart",
857 .dma_mask = &uart0_dmamask,
858 .coherent_dma_mask = DMA_BIT_MASK(32),
859 .platform_data = &uart0_data,
861 .resource = uart0_resources,
862 .num_resources = ARRAY_SIZE(uart0_resources),
865 static inline void configure_usart0_pins(unsigned pins)
867 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
868 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
870 if (pins & ATMEL_UART_CTS)
871 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
873 if (pins & ATMEL_UART_RTS) {
875 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
876 * We need to drive the pin manually. Default is off (RTS is active low).
878 at91_set_gpio_output(AT91_PIN_PA21, 1);
882 static struct resource uart1_resources[] = {
884 .start = AT91RM9200_BASE_US1,
885 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
886 .flags = IORESOURCE_MEM,
889 .start = AT91RM9200_ID_US1,
890 .end = AT91RM9200_ID_US1,
891 .flags = IORESOURCE_IRQ,
895 static struct atmel_uart_data uart1_data = {
900 static u64 uart1_dmamask = DMA_BIT_MASK(32);
902 static struct platform_device at91rm9200_uart1_device = {
903 .name = "atmel_usart",
906 .dma_mask = &uart1_dmamask,
907 .coherent_dma_mask = DMA_BIT_MASK(32),
908 .platform_data = &uart1_data,
910 .resource = uart1_resources,
911 .num_resources = ARRAY_SIZE(uart1_resources),
914 static inline void configure_usart1_pins(unsigned pins)
916 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
917 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
919 if (pins & ATMEL_UART_RI)
920 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
921 if (pins & ATMEL_UART_DTR)
922 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
923 if (pins & ATMEL_UART_DCD)
924 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
925 if (pins & ATMEL_UART_CTS)
926 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
927 if (pins & ATMEL_UART_DSR)
928 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
929 if (pins & ATMEL_UART_RTS)
930 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
933 static struct resource uart2_resources[] = {
935 .start = AT91RM9200_BASE_US2,
936 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
937 .flags = IORESOURCE_MEM,
940 .start = AT91RM9200_ID_US2,
941 .end = AT91RM9200_ID_US2,
942 .flags = IORESOURCE_IRQ,
946 static struct atmel_uart_data uart2_data = {
951 static u64 uart2_dmamask = DMA_BIT_MASK(32);
953 static struct platform_device at91rm9200_uart2_device = {
954 .name = "atmel_usart",
957 .dma_mask = &uart2_dmamask,
958 .coherent_dma_mask = DMA_BIT_MASK(32),
959 .platform_data = &uart2_data,
961 .resource = uart2_resources,
962 .num_resources = ARRAY_SIZE(uart2_resources),
965 static inline void configure_usart2_pins(unsigned pins)
967 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
968 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
970 if (pins & ATMEL_UART_CTS)
971 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
972 if (pins & ATMEL_UART_RTS)
973 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
976 static struct resource uart3_resources[] = {
978 .start = AT91RM9200_BASE_US3,
979 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
980 .flags = IORESOURCE_MEM,
983 .start = AT91RM9200_ID_US3,
984 .end = AT91RM9200_ID_US3,
985 .flags = IORESOURCE_IRQ,
989 static struct atmel_uart_data uart3_data = {
994 static u64 uart3_dmamask = DMA_BIT_MASK(32);
996 static struct platform_device at91rm9200_uart3_device = {
997 .name = "atmel_usart",
1000 .dma_mask = &uart3_dmamask,
1001 .coherent_dma_mask = DMA_BIT_MASK(32),
1002 .platform_data = &uart3_data,
1004 .resource = uart3_resources,
1005 .num_resources = ARRAY_SIZE(uart3_resources),
1008 static inline void configure_usart3_pins(unsigned pins)
1010 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1011 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1013 if (pins & ATMEL_UART_CTS)
1014 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1015 if (pins & ATMEL_UART_RTS)
1016 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1019 static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1020 struct platform_device *atmel_default_console_device; /* the serial console device */
1022 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
1026 /* Fill in list of supported UARTs */
1027 for (i = 0; i < config->nr_tty; i++) {
1028 switch (config->tty_map[i]) {
1030 configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
1031 at91_uarts[i] = &at91rm9200_uart0_device;
1032 at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
1035 configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
1036 at91_uarts[i] = &at91rm9200_uart1_device;
1037 at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
1040 configure_usart2_pins(0);
1041 at91_uarts[i] = &at91rm9200_uart2_device;
1042 at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
1045 configure_usart3_pins(0);
1046 at91_uarts[i] = &at91rm9200_uart3_device;
1047 at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
1050 configure_dbgu_pins();
1051 at91_uarts[i] = &at91rm9200_dbgu_device;
1052 at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
1057 at91_uarts[i]->id = i; /* update ID number to mapped ID */
1060 /* Set serial console device */
1061 if (config->console_tty < ATMEL_MAX_UART)
1062 atmel_default_console_device = at91_uarts[config->console_tty];
1063 if (!atmel_default_console_device)
1064 printk(KERN_INFO "AT91: No default serial console defined.\n");
1067 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1069 struct platform_device *pdev;
1073 pdev = &at91rm9200_dbgu_device;
1074 configure_dbgu_pins();
1075 at91_clock_associate("mck", &pdev->dev, "usart");
1077 case AT91RM9200_ID_US0:
1078 pdev = &at91rm9200_uart0_device;
1079 configure_usart0_pins(pins);
1080 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1082 case AT91RM9200_ID_US1:
1083 pdev = &at91rm9200_uart1_device;
1084 configure_usart1_pins(pins);
1085 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1087 case AT91RM9200_ID_US2:
1088 pdev = &at91rm9200_uart2_device;
1089 configure_usart2_pins(pins);
1090 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1092 case AT91RM9200_ID_US3:
1093 pdev = &at91rm9200_uart3_device;
1094 configure_usart3_pins(pins);
1095 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1100 pdev->id = portnr; /* update to mapped ID */
1102 if (portnr < ATMEL_MAX_UART)
1103 at91_uarts[portnr] = pdev;
1106 void __init at91_set_serial_console(unsigned portnr)
1108 if (portnr < ATMEL_MAX_UART)
1109 atmel_default_console_device = at91_uarts[portnr];
1110 if (!atmel_default_console_device)
1111 printk(KERN_INFO "AT91: No default serial console defined.\n");
1114 void __init at91_add_device_serial(void)
1118 for (i = 0; i < ATMEL_MAX_UART; i++) {
1120 platform_device_register(at91_uarts[i]);
1124 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1125 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1126 void __init at91_set_serial_console(unsigned portnr) {}
1127 void __init at91_add_device_serial(void) {}
1131 /* -------------------------------------------------------------------- */
1134 * These devices are always present and don't need any board-specific
1137 static int __init at91_add_standard_devices(void)
1139 at91_add_device_rtc();
1140 at91_add_device_watchdog();
1144 arch_initcall(at91_add_standard_devices);