2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 get_irqnr_preamble r5, lr
31 1: get_irqnr_and_base r0, r6, r5, lr
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
46 test_for_ipi r0, r6, r5, lr
51 #ifdef CONFIG_LOCAL_TIMERS
52 test_for_ltirq r0, r6, r5, lr
62 .section .kprobes.text,"ax",%progbits
68 * Invalid mode handlers
70 .macro inv_entry, reason
71 sub sp, sp, #S_FRAME_SIZE
77 inv_entry BAD_PREFETCH
89 inv_entry BAD_UNDEFINSTR
92 @ XXX fall through to common_invalid
96 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
102 add r0, sp, #S_PC @ here for interlock avoidance
103 mov r7, #-1 @ "" "" "" ""
104 str r4, [sp] @ save preserved r0
105 stmia r0, {r5 - r7} @ lr_<exception>,
106 @ cpsr_<exception>, "old_r0"
115 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
116 #define SPFIX(code...) code
118 #define SPFIX(code...)
121 .macro svc_entry, stack_hole=0
122 sub sp, sp, #(S_FRAME_SIZE + \stack_hole)
124 SPFIX( bicne sp, sp, #4 )
128 add r5, sp, #S_SP @ here for interlock avoidance
129 mov r4, #-1 @ "" "" "" ""
130 add r0, sp, #(S_FRAME_SIZE + \stack_hole)
131 SPFIX( addne r0, r0, #4 )
132 str r1, [sp] @ save the "real" r0 copied
133 @ from the exception stack
138 @ We are now ready to fill in the remaining blanks on the stack:
142 @ r2 - lr_<exception>, already fixed up for correct return/restart
143 @ r3 - spsr_<exception>
144 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
154 @ get ready to re-enable interrupts if appropriate
158 biceq r9, r9, #PSR_I_BIT
161 @ Call the processor-specific abort handler:
163 @ r2 - aborted context pc
164 @ r3 - aborted context cpsr
166 @ The abort handler must return the aborted address in r0, and
167 @ the fault status register in r1. r9 must be preserved.
178 @ set desired IRQ state, then call main handler
185 @ IRQs off again before pulling preserved data off the stack
190 @ restore SPSR and restart the instruction
194 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
200 #ifdef CONFIG_TRACE_IRQFLAGS
201 bl trace_hardirqs_off
203 #ifdef CONFIG_PREEMPT
205 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
206 add r7, r8, #1 @ increment it
207 str r7, [tsk, #TI_PREEMPT]
211 #ifdef CONFIG_PREEMPT
212 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
213 ldr r0, [tsk, #TI_FLAGS] @ get flags
214 teq r8, #0 @ if preempt count != 0
215 movne r0, #0 @ force flags to 0
216 tst r0, #_TIF_NEED_RESCHED
219 ldr r0, [sp, #S_PSR] @ irqs are already disabled
221 #ifdef CONFIG_TRACE_IRQFLAGS
223 bleq trace_hardirqs_on
225 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
229 #ifdef CONFIG_PREEMPT
232 1: bl preempt_schedule_irq @ irq en/disable is done inside
233 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
234 tst r0, #_TIF_NEED_RESCHED
235 moveq pc, r8 @ go again
241 #ifdef CONFIG_KPROBES
242 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
243 @ it obviously needs free stack space which then will belong to
251 @ call emulation code, which returns using r9 if it has emulated
252 @ the instruction, or the more conventional lr if we are to treat
253 @ this as a real undefined instruction
261 mov r0, sp @ struct pt_regs *regs
265 @ IRQs off again before pulling preserved data off the stack
270 @ restore SPSR and restart the instruction
272 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
274 ldmia sp, {r0 - pc}^ @ Restore SVC registers
281 @ re-enable interrupts if appropriate
285 biceq r9, r9, #PSR_I_BIT
289 @ set args, then call main handler
291 @ r0 - address of faulting instruction
292 @ r1 - pointer to registers on stack
294 mov r0, r2 @ address (pc)
296 bl do_PrefetchAbort @ call abort handler
299 @ IRQs off again before pulling preserved data off the stack
304 @ restore SPSR and restart the instruction
308 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
323 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
326 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
327 #error "sizeof(struct pt_regs) must be a multiple of 8"
331 sub sp, sp, #S_FRAME_SIZE
335 add r0, sp, #S_PC @ here for interlock avoidance
336 mov r4, #-1 @ "" "" "" ""
338 str r1, [sp] @ save the "real" r0 copied
339 @ from the exception stack
342 @ We are now ready to fill in the remaining blanks on the stack:
344 @ r2 - lr_<exception>, already fixed up for correct return/restart
345 @ r3 - spsr_<exception>
346 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
348 @ Also, separately save sp_usr and lr_usr
354 @ Enable the alignment trap while in kernel mode
359 @ Clear FP to mark the first stack frame
364 .macro kuser_cmpxchg_check
365 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
367 #warning "NPTL on non MMU needs fixing"
369 @ Make sure our user space atomic helper is restarted
370 @ if it was interrupted in a critical region. Here we
371 @ perform a quick test inline since it should be false
372 @ 99.9999% of the time. The rest is done out of line.
374 blhs kuser_cmpxchg_fixup
385 @ Call the processor-specific abort handler:
387 @ r2 - aborted context pc
388 @ r3 - aborted context cpsr
390 @ The abort handler must return the aborted address in r0, and
391 @ the fault status register in r1.
402 @ IRQs on, then call the main handler
406 adr lr, ret_from_exception
414 #ifdef CONFIG_TRACE_IRQFLAGS
415 bl trace_hardirqs_off
418 #ifdef CONFIG_PREEMPT
419 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
420 add r7, r8, #1 @ increment it
421 str r7, [tsk, #TI_PREEMPT]
425 #ifdef CONFIG_PREEMPT
426 ldr r0, [tsk, #TI_PREEMPT]
427 str r8, [tsk, #TI_PREEMPT]
431 #ifdef CONFIG_TRACE_IRQFLAGS
444 tst r3, #PSR_T_BIT @ Thumb mode?
445 bne __und_usr_unknown @ ignore FP
449 @ fall through to the emulation code, which returns using r9 if
450 @ it has emulated the instruction, or the more conventional lr
451 @ if we are to treat this as a real undefined instruction
455 adr r9, ret_from_exception
456 adr lr, __und_usr_unknown
459 @ fallthrough to call_fpe
463 * The out of line fixup for the ldrt above.
465 .section .fixup, "ax"
468 .section __ex_table,"a"
473 * Check whether the instruction is a co-processor instruction.
474 * If yes, we need to call the relevant co-processor handler.
476 * Note that we don't do a full check here for the co-processor
477 * instructions; all instructions with bit 27 set are well
478 * defined. The only instructions that should fault are the
479 * co-processor instructions. However, we have to watch out
480 * for the ARM6/ARM7 SWI bug.
482 * NEON is a special case that has to be handled here. Not all
483 * NEON instructions are co-processor instructions, so we have
484 * to make a special case of checking for them. Plus, there's
485 * five groups of them, so we have a table of mask/opcode pairs
486 * to check against, and if any match then we branch off into the
489 * Emulators may wish to make use of the following registers:
490 * r0 = instruction opcode.
492 * r9 = normal "successful" return address
493 * r10 = this threads thread_info structure.
494 * lr = unrecognised instruction return address
498 adr r6, .LCneon_opcodes
500 ldr r7, [r6], #4 @ mask value
501 cmp r7, #0 @ end mask?
504 ldr r7, [r6], #4 @ opcode bits matching in mask
505 cmp r8, r7 @ NEON instruction?
509 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
510 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
511 b do_vfp @ let VFP handler handle this
514 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
515 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
516 and r8, r0, #0x0f000000 @ mask out op-code bits
517 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
520 get_thread_info r10 @ get current thread
521 and r8, r0, #0x00000f00 @ mask out CP number
523 add r6, r10, #TI_USED_CP
524 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
526 @ Test if we need to give access to iWMMXt coprocessors
527 ldr r5, [r10, #TI_FLAGS]
528 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
529 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
530 bcs iwmmxt_task_enable
532 add pc, pc, r8, lsr #6
536 b do_fpe @ CP#1 (FPE)
537 b do_fpe @ CP#2 (FPE)
540 b crunch_task_enable @ CP#4 (MaverickCrunch)
541 b crunch_task_enable @ CP#5 (MaverickCrunch)
542 b crunch_task_enable @ CP#6 (MaverickCrunch)
552 b do_vfp @ CP#10 (VFP)
553 b do_vfp @ CP#11 (VFP)
555 mov pc, lr @ CP#10 (VFP)
556 mov pc, lr @ CP#11 (VFP)
560 mov pc, lr @ CP#14 (Debug)
561 mov pc, lr @ CP#15 (Control)
567 .word 0xfe000000 @ mask
568 .word 0xf2000000 @ opcode
570 .word 0xff100000 @ mask
571 .word 0xf4000000 @ opcode
573 .word 0x00000000 @ mask
574 .word 0x00000000 @ opcode
580 add r10, r10, #TI_FPSTATE @ r10 = workspace
581 ldr pc, [r4] @ Call FP module USR entry point
584 * The FP module is called with these registers set:
587 * r9 = normal "successful" return address
589 * lr = unrecognised FP instruction return address
601 adr lr, ret_from_exception
608 enable_irq @ Enable interrupts
609 mov r0, r2 @ address (pc)
611 bl do_PrefetchAbort @ call abort handler
614 * This is the return code to user mode for abort handlers
616 ENTRY(ret_from_exception)
622 * Register switch for ARMv3 and ARMv4 processors
623 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
624 * previous and next are guaranteed not to be the same.
627 add ip, r1, #TI_CPU_SAVE
628 ldr r3, [r2, #TI_TP_VALUE]
629 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
631 ldr r6, [r2, #TI_CPU_DOMAIN]
633 #if __LINUX_ARM_ARCH__ >= 6
634 #ifdef CONFIG_CPU_32v6K
637 strex r5, r4, [ip] @ Clear exclusive monitor
640 #if defined(CONFIG_HAS_TLS_REG)
641 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
642 #elif !defined(CONFIG_TLS_REG_EMUL)
644 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
647 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
650 add r4, r2, #TI_CPU_SAVE
651 ldr r0, =thread_notify_head
652 mov r1, #THREAD_NOTIFY_SWITCH
653 bl atomic_notifier_call_chain
655 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
662 * These are segment of kernel provided user code reachable from user space
663 * at a fixed address in kernel memory. This is used to provide user space
664 * with some operations which require kernel help because of unimplemented
665 * native feature and/or instructions in many ARM CPUs. The idea is for
666 * this code to be executed directly in user mode for best efficiency but
667 * which is too intimate with the kernel counter part to be left to user
668 * libraries. In fact this code might even differ from one CPU to another
669 * depending on the available instruction set and restrictions like on
670 * SMP systems. In other words, the kernel reserves the right to change
671 * this code as needed without warning. Only the entry points and their
672 * results are guaranteed to be stable.
674 * Each segment is 32-byte aligned and will be moved to the top of the high
675 * vector page. New segments (if ever needed) must be added in front of
676 * existing ones. This mechanism should be used only for things that are
677 * really small and justified, and not be abused freely.
679 * User space is expected to implement those things inline when optimizing
680 * for a processor that has the necessary native support, but only if such
681 * resulting binaries are already to be incompatible with earlier ARM
682 * processors due to the use of unsupported instructions other than what
683 * is provided here. In other words don't make binaries unable to run on
684 * earlier processors just for the sake of not using these kernel helpers
685 * if your compiled code is not going to use the new instructions for other
690 #ifdef CONFIG_ARM_THUMB
698 .globl __kuser_helper_start
699 __kuser_helper_start:
702 * Reference prototype:
704 * void __kernel_memory_barrier(void)
708 * lr = return address
718 * Definition and user space usage example:
720 * typedef void (__kernel_dmb_t)(void);
721 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
723 * Apply any needed memory barrier to preserve consistency with data modified
724 * manually and __kuser_cmpxchg usage.
726 * This could be used as follows:
728 * #define __kernel_dmb() \
729 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
730 * : : : "r0", "lr","cc" )
733 __kuser_memory_barrier: @ 0xffff0fa0
735 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
736 mcr p15, 0, r0, c7, c10, 5 @ dmb
743 * Reference prototype:
745 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
752 * lr = return address
756 * r0 = returned value (zero or non-zero)
757 * C flag = set if r0 == 0, clear if r0 != 0
763 * Definition and user space usage example:
765 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
766 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
768 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
769 * Return zero if *ptr was changed or non-zero if no exchange happened.
770 * The C flag is also set if *ptr was changed to allow for assembly
771 * optimization in the calling code.
775 * - This routine already includes memory barriers as needed.
777 * For example, a user space atomic_add implementation could look like this:
779 * #define atomic_add(ptr, val) \
780 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
781 * register unsigned int __result asm("r1"); \
783 * "1: @ atomic_add\n\t" \
784 * "ldr r0, [r2]\n\t" \
785 * "mov r3, #0xffff0fff\n\t" \
786 * "add lr, pc, #4\n\t" \
787 * "add r1, r0, %2\n\t" \
788 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
790 * : "=&r" (__result) \
791 * : "r" (__ptr), "rIL" (val) \
792 * : "r0","r3","ip","lr","cc","memory" ); \
796 __kuser_cmpxchg: @ 0xffff0fc0
798 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
801 * Poor you. No fast solution possible...
802 * The kernel itself must perform the operation.
803 * A special ghost syscall is used for that (see traps.c).
806 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
811 #elif __LINUX_ARM_ARCH__ < 6
816 * The only thing that can break atomicity in this cmpxchg
817 * implementation is either an IRQ or a data abort exception
818 * causing another process/thread to be scheduled in the middle
819 * of the critical sequence. To prevent this, code is added to
820 * the IRQ and data abort exception handlers to set the pc back
821 * to the beginning of the critical section if it is found to be
822 * within that critical section (see kuser_cmpxchg_fixup).
824 1: ldr r3, [r2] @ load current val
825 subs r3, r3, r0 @ compare with oldval
826 2: streq r1, [r2] @ store newval if eq
827 rsbs r0, r3, #0 @ set return val and C flag
832 @ Called from kuser_cmpxchg_check macro.
833 @ r2 = address of interrupted insn (must be preserved).
834 @ sp = saved regs. r7 and r8 are clobbered.
835 @ 1b = first critical insn, 2b = last critical insn.
836 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
838 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
840 rsbcss r8, r8, #(2b - 1b)
841 strcs r7, [sp, #S_PC]
846 #warning "NPTL on non MMU needs fixing"
855 mcr p15, 0, r0, c7, c10, 5 @ dmb
863 /* beware -- each __kuser slot must be 8 instructions max */
865 b __kuser_memory_barrier
875 * Reference prototype:
877 * int __kernel_get_tls(void)
881 * lr = return address
891 * Definition and user space usage example:
893 * typedef int (__kernel_get_tls_t)(void);
894 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
896 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
898 * This could be used as follows:
900 * #define __kernel_get_tls() \
901 * ({ register unsigned int __val asm("r0"); \
902 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
903 * : "=r" (__val) : : "lr","cc" ); \
907 __kuser_get_tls: @ 0xffff0fe0
909 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
910 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
912 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
917 .word 0 @ pad up to __kuser_helper_version
921 * Reference declaration:
923 * extern unsigned int __kernel_helper_version;
925 * Definition and user space usage example:
927 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
929 * User space may read this to determine the curent number of helpers
933 __kuser_helper_version: @ 0xffff0ffc
934 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
936 .globl __kuser_helper_end
943 * This code is copied to 0xffff0200 so we can use branches in the
944 * vectors, rather than ldr's. Note that this code must not
945 * exceed 0x300 bytes.
947 * Common stub entry macro:
948 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
950 * SP points to a minimal amount of processor-private memory, the address
951 * of which is copied into r0 for the mode specific abort handler.
953 .macro vector_stub, name, mode, correction=0
958 sub lr, lr, #\correction
962 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
965 stmia sp, {r0, lr} @ save r0, lr
967 str lr, [sp, #8] @ save spsr
970 @ Prepare for SVC32 mode. IRQs remain disabled.
973 eor r0, r0, #(\mode ^ SVC_MODE)
977 @ the branch table must immediately follow this code
981 ldr lr, [pc, lr, lsl #2]
982 movs pc, lr @ branch to handler in SVC mode
988 * Interrupt dispatcher
990 vector_stub irq, IRQ_MODE, 4
992 .long __irq_usr @ 0 (USR_26 / USR_32)
993 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
994 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
995 .long __irq_svc @ 3 (SVC_26 / SVC_32)
996 .long __irq_invalid @ 4
997 .long __irq_invalid @ 5
998 .long __irq_invalid @ 6
999 .long __irq_invalid @ 7
1000 .long __irq_invalid @ 8
1001 .long __irq_invalid @ 9
1002 .long __irq_invalid @ a
1003 .long __irq_invalid @ b
1004 .long __irq_invalid @ c
1005 .long __irq_invalid @ d
1006 .long __irq_invalid @ e
1007 .long __irq_invalid @ f
1010 * Data abort dispatcher
1011 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1013 vector_stub dabt, ABT_MODE, 8
1015 .long __dabt_usr @ 0 (USR_26 / USR_32)
1016 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1017 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1018 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1019 .long __dabt_invalid @ 4
1020 .long __dabt_invalid @ 5
1021 .long __dabt_invalid @ 6
1022 .long __dabt_invalid @ 7
1023 .long __dabt_invalid @ 8
1024 .long __dabt_invalid @ 9
1025 .long __dabt_invalid @ a
1026 .long __dabt_invalid @ b
1027 .long __dabt_invalid @ c
1028 .long __dabt_invalid @ d
1029 .long __dabt_invalid @ e
1030 .long __dabt_invalid @ f
1033 * Prefetch abort dispatcher
1034 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1036 vector_stub pabt, ABT_MODE, 4
1038 .long __pabt_usr @ 0 (USR_26 / USR_32)
1039 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1040 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1041 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1042 .long __pabt_invalid @ 4
1043 .long __pabt_invalid @ 5
1044 .long __pabt_invalid @ 6
1045 .long __pabt_invalid @ 7
1046 .long __pabt_invalid @ 8
1047 .long __pabt_invalid @ 9
1048 .long __pabt_invalid @ a
1049 .long __pabt_invalid @ b
1050 .long __pabt_invalid @ c
1051 .long __pabt_invalid @ d
1052 .long __pabt_invalid @ e
1053 .long __pabt_invalid @ f
1056 * Undef instr entry dispatcher
1057 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1059 vector_stub und, UND_MODE
1061 .long __und_usr @ 0 (USR_26 / USR_32)
1062 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1063 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1064 .long __und_svc @ 3 (SVC_26 / SVC_32)
1065 .long __und_invalid @ 4
1066 .long __und_invalid @ 5
1067 .long __und_invalid @ 6
1068 .long __und_invalid @ 7
1069 .long __und_invalid @ 8
1070 .long __und_invalid @ 9
1071 .long __und_invalid @ a
1072 .long __und_invalid @ b
1073 .long __und_invalid @ c
1074 .long __und_invalid @ d
1075 .long __und_invalid @ e
1076 .long __und_invalid @ f
1080 /*=============================================================================
1082 *-----------------------------------------------------------------------------
1083 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1084 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1085 * Basically to switch modes, we *HAVE* to clobber one register... brain
1086 * damage alert! I don't think that we can execute any code in here in any
1087 * other mode than FIQ... Ok you can switch to another mode, but you can't
1088 * get out of that mode without clobbering one register.
1094 /*=============================================================================
1095 * Address exception handler
1096 *-----------------------------------------------------------------------------
1097 * These aren't too critical.
1098 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1105 * We group all the following data together to optimise
1106 * for CPUs with separate I & D caches.
1116 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1118 .globl __vectors_start
1121 b vector_und + stubs_offset
1122 ldr pc, .LCvswi + stubs_offset
1123 b vector_pabt + stubs_offset
1124 b vector_dabt + stubs_offset
1125 b vector_addrexcptn + stubs_offset
1126 b vector_irq + stubs_offset
1127 b vector_fiq + stubs_offset
1129 .globl __vectors_end
1135 .globl cr_no_alignment
projects / linux-2.6 / blob