2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
15 * it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 get_irqnr_preamble r5, lr
31 1: get_irqnr_and_base r0, r6, r5, lr
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
46 test_for_ipi r0, r6, r5, lr
51 #ifdef CONFIG_LOCAL_TIMERS
52 test_for_ltirq r0, r6, r5, lr
62 * Invalid mode handlers
64 .macro inv_entry, reason
65 sub sp, sp, #S_FRAME_SIZE
71 inv_entry BAD_PREFETCH
83 inv_entry BAD_UNDEFINSTR
86 @ XXX fall through to common_invalid
90 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
96 add r0, sp, #S_PC @ here for interlock avoidance
97 mov r7, #-1 @ "" "" "" ""
98 str r4, [sp] @ save preserved r0
99 stmia r0, {r5 - r7} @ lr_<exception>,
100 @ cpsr_<exception>, "old_r0"
109 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
110 #define SPFIX(code...) code
112 #define SPFIX(code...)
115 .macro svc_entry, stack_hole=0
116 sub sp, sp, #(S_FRAME_SIZE + \stack_hole)
118 SPFIX( bicne sp, sp, #4 )
122 add r5, sp, #S_SP @ here for interlock avoidance
123 mov r4, #-1 @ "" "" "" ""
124 add r0, sp, #(S_FRAME_SIZE + \stack_hole)
125 SPFIX( addne r0, r0, #4 )
126 str r1, [sp] @ save the "real" r0 copied
127 @ from the exception stack
132 @ We are now ready to fill in the remaining blanks on the stack:
136 @ r2 - lr_<exception>, already fixed up for correct return/restart
137 @ r3 - spsr_<exception>
138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
148 @ get ready to re-enable interrupts if appropriate
152 biceq r9, r9, #PSR_I_BIT
155 @ Call the processor-specific abort handler:
157 @ r2 - aborted context pc
158 @ r3 - aborted context cpsr
160 @ The abort handler must return the aborted address in r0, and
161 @ the fault status register in r1. r9 must be preserved.
172 @ set desired IRQ state, then call main handler
179 @ IRQs off again before pulling preserved data off the stack
184 @ restore SPSR and restart the instruction
188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
194 #ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
197 #ifdef CONFIG_PREEMPT
199 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
200 add r7, r8, #1 @ increment it
201 str r7, [tsk, #TI_PREEMPT]
205 #ifdef CONFIG_PREEMPT
206 ldr r0, [tsk, #TI_FLAGS] @ get flags
207 tst r0, #_TIF_NEED_RESCHED
210 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
211 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
213 strne r0, [r0, -r0] @ bug()
215 ldr r0, [sp, #S_PSR] @ irqs are already disabled
217 #ifdef CONFIG_TRACE_IRQFLAGS
219 bleq trace_hardirqs_on
221 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
225 #ifdef CONFIG_PREEMPT
227 teq r8, #0 @ was preempt count = 0
228 ldreq r6, .LCirq_stat
230 ldr r0, [r6, #4] @ local_irq_count
231 ldr r1, [r6, #8] @ local_bh_count
234 mov r7, #0 @ preempt_schedule_irq
235 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
236 1: bl preempt_schedule_irq @ irq en/disable is done inside
237 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
238 tst r0, #_TIF_NEED_RESCHED
239 beq preempt_return @ go again
245 #ifdef CONFIG_KPROBES
246 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
247 @ it obviously needs free stack space which then will belong to
255 @ call emulation code, which returns using r9 if it has emulated
256 @ the instruction, or the more conventional lr if we are to treat
257 @ this as a real undefined instruction
265 mov r0, sp @ struct pt_regs *regs
269 @ IRQs off again before pulling preserved data off the stack
274 @ restore SPSR and restart the instruction
276 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
278 ldmia sp, {r0 - pc}^ @ Restore SVC registers
285 @ re-enable interrupts if appropriate
289 biceq r9, r9, #PSR_I_BIT
293 @ set args, then call main handler
295 @ r0 - address of faulting instruction
296 @ r1 - pointer to registers on stack
298 mov r0, r2 @ address (pc)
300 bl do_PrefetchAbort @ call abort handler
303 @ IRQs off again before pulling preserved data off the stack
308 @ restore SPSR and restart the instruction
312 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
323 #ifdef CONFIG_PREEMPT
331 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
334 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
335 #error "sizeof(struct pt_regs) must be a multiple of 8"
339 sub sp, sp, #S_FRAME_SIZE
343 add r0, sp, #S_PC @ here for interlock avoidance
344 mov r4, #-1 @ "" "" "" ""
346 str r1, [sp] @ save the "real" r0 copied
347 @ from the exception stack
350 @ We are now ready to fill in the remaining blanks on the stack:
352 @ r2 - lr_<exception>, already fixed up for correct return/restart
353 @ r3 - spsr_<exception>
354 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
356 @ Also, separately save sp_usr and lr_usr
362 @ Enable the alignment trap while in kernel mode
367 @ Clear FP to mark the first stack frame
372 .macro kuser_cmpxchg_check
373 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
375 #warning "NPTL on non MMU needs fixing"
377 @ Make sure our user space atomic helper is restarted
378 @ if it was interrupted in a critical region. Here we
379 @ perform a quick test inline since it should be false
380 @ 99.9999% of the time. The rest is done out of line.
382 blhs kuser_cmpxchg_fixup
393 @ Call the processor-specific abort handler:
395 @ r2 - aborted context pc
396 @ r3 - aborted context cpsr
398 @ The abort handler must return the aborted address in r0, and
399 @ the fault status register in r1.
410 @ IRQs on, then call the main handler
414 adr lr, ret_from_exception
422 #ifdef CONFIG_TRACE_IRQFLAGS
423 bl trace_hardirqs_off
426 #ifdef CONFIG_PREEMPT
427 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
428 add r7, r8, #1 @ increment it
429 str r7, [tsk, #TI_PREEMPT]
433 #ifdef CONFIG_PREEMPT
434 ldr r0, [tsk, #TI_PREEMPT]
435 str r8, [tsk, #TI_PREEMPT]
439 #ifdef CONFIG_TRACE_IRQFLAGS
452 tst r3, #PSR_T_BIT @ Thumb mode?
453 bne __und_usr_unknown @ ignore FP
457 @ fall through to the emulation code, which returns using r9 if
458 @ it has emulated the instruction, or the more conventional lr
459 @ if we are to treat this as a real undefined instruction
463 adr r9, ret_from_exception
464 adr lr, __und_usr_unknown
467 @ fallthrough to call_fpe
471 * The out of line fixup for the ldrt above.
473 .section .fixup, "ax"
476 .section __ex_table,"a"
481 * Check whether the instruction is a co-processor instruction.
482 * If yes, we need to call the relevant co-processor handler.
484 * Note that we don't do a full check here for the co-processor
485 * instructions; all instructions with bit 27 set are well
486 * defined. The only instructions that should fault are the
487 * co-processor instructions. However, we have to watch out
488 * for the ARM6/ARM7 SWI bug.
490 * Emulators may wish to make use of the following registers:
491 * r0 = instruction opcode.
493 * r9 = normal "successful" return address
494 * r10 = this threads thread_info structure.
495 * lr = unrecognised instruction return address
498 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
499 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
500 and r8, r0, #0x0f000000 @ mask out op-code bits
501 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
504 get_thread_info r10 @ get current thread
505 and r8, r0, #0x00000f00 @ mask out CP number
507 add r6, r10, #TI_USED_CP
508 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
510 @ Test if we need to give access to iWMMXt coprocessors
511 ldr r5, [r10, #TI_FLAGS]
512 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
513 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
514 bcs iwmmxt_task_enable
516 add pc, pc, r8, lsr #6
520 b do_fpe @ CP#1 (FPE)
521 b do_fpe @ CP#2 (FPE)
524 b crunch_task_enable @ CP#4 (MaverickCrunch)
525 b crunch_task_enable @ CP#5 (MaverickCrunch)
526 b crunch_task_enable @ CP#6 (MaverickCrunch)
536 b do_vfp @ CP#10 (VFP)
537 b do_vfp @ CP#11 (VFP)
539 mov pc, lr @ CP#10 (VFP)
540 mov pc, lr @ CP#11 (VFP)
544 mov pc, lr @ CP#14 (Debug)
545 mov pc, lr @ CP#15 (Control)
550 add r10, r10, #TI_FPSTATE @ r10 = workspace
551 ldr pc, [r4] @ Call FP module USR entry point
554 * The FP module is called with these registers set:
557 * r9 = normal "successful" return address
559 * lr = unrecognised FP instruction return address
571 adr lr, ret_from_exception
578 enable_irq @ Enable interrupts
579 mov r0, r2 @ address (pc)
581 bl do_PrefetchAbort @ call abort handler
584 * This is the return code to user mode for abort handlers
586 ENTRY(ret_from_exception)
592 * Register switch for ARMv3 and ARMv4 processors
593 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
594 * previous and next are guaranteed not to be the same.
597 add ip, r1, #TI_CPU_SAVE
598 ldr r3, [r2, #TI_TP_VALUE]
599 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
601 ldr r6, [r2, #TI_CPU_DOMAIN]
603 #if __LINUX_ARM_ARCH__ >= 6
604 #ifdef CONFIG_CPU_32v6K
607 strex r5, r4, [ip] @ Clear exclusive monitor
610 #if defined(CONFIG_HAS_TLS_REG)
611 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
612 #elif !defined(CONFIG_TLS_REG_EMUL)
614 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
617 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
620 add r4, r2, #TI_CPU_SAVE
621 ldr r0, =thread_notify_head
622 mov r1, #THREAD_NOTIFY_SWITCH
623 bl atomic_notifier_call_chain
625 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
632 * These are segment of kernel provided user code reachable from user space
633 * at a fixed address in kernel memory. This is used to provide user space
634 * with some operations which require kernel help because of unimplemented
635 * native feature and/or instructions in many ARM CPUs. The idea is for
636 * this code to be executed directly in user mode for best efficiency but
637 * which is too intimate with the kernel counter part to be left to user
638 * libraries. In fact this code might even differ from one CPU to another
639 * depending on the available instruction set and restrictions like on
640 * SMP systems. In other words, the kernel reserves the right to change
641 * this code as needed without warning. Only the entry points and their
642 * results are guaranteed to be stable.
644 * Each segment is 32-byte aligned and will be moved to the top of the high
645 * vector page. New segments (if ever needed) must be added in front of
646 * existing ones. This mechanism should be used only for things that are
647 * really small and justified, and not be abused freely.
649 * User space is expected to implement those things inline when optimizing
650 * for a processor that has the necessary native support, but only if such
651 * resulting binaries are already to be incompatible with earlier ARM
652 * processors due to the use of unsupported instructions other than what
653 * is provided here. In other words don't make binaries unable to run on
654 * earlier processors just for the sake of not using these kernel helpers
655 * if your compiled code is not going to use the new instructions for other
660 #ifdef CONFIG_ARM_THUMB
668 .globl __kuser_helper_start
669 __kuser_helper_start:
672 * Reference prototype:
674 * void __kernel_memory_barrier(void)
678 * lr = return address
688 * Definition and user space usage example:
690 * typedef void (__kernel_dmb_t)(void);
691 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
693 * Apply any needed memory barrier to preserve consistency with data modified
694 * manually and __kuser_cmpxchg usage.
696 * This could be used as follows:
698 * #define __kernel_dmb() \
699 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
700 * : : : "r0", "lr","cc" )
703 __kuser_memory_barrier: @ 0xffff0fa0
705 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
706 mcr p15, 0, r0, c7, c10, 5 @ dmb
713 * Reference prototype:
715 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
722 * lr = return address
726 * r0 = returned value (zero or non-zero)
727 * C flag = set if r0 == 0, clear if r0 != 0
733 * Definition and user space usage example:
735 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
736 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
738 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
739 * Return zero if *ptr was changed or non-zero if no exchange happened.
740 * The C flag is also set if *ptr was changed to allow for assembly
741 * optimization in the calling code.
745 * - This routine already includes memory barriers as needed.
747 * For example, a user space atomic_add implementation could look like this:
749 * #define atomic_add(ptr, val) \
750 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
751 * register unsigned int __result asm("r1"); \
753 * "1: @ atomic_add\n\t" \
754 * "ldr r0, [r2]\n\t" \
755 * "mov r3, #0xffff0fff\n\t" \
756 * "add lr, pc, #4\n\t" \
757 * "add r1, r0, %2\n\t" \
758 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
760 * : "=&r" (__result) \
761 * : "r" (__ptr), "rIL" (val) \
762 * : "r0","r3","ip","lr","cc","memory" ); \
766 __kuser_cmpxchg: @ 0xffff0fc0
768 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
771 * Poor you. No fast solution possible...
772 * The kernel itself must perform the operation.
773 * A special ghost syscall is used for that (see traps.c).
776 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
781 #elif __LINUX_ARM_ARCH__ < 6
786 * The only thing that can break atomicity in this cmpxchg
787 * implementation is either an IRQ or a data abort exception
788 * causing another process/thread to be scheduled in the middle
789 * of the critical sequence. To prevent this, code is added to
790 * the IRQ and data abort exception handlers to set the pc back
791 * to the beginning of the critical section if it is found to be
792 * within that critical section (see kuser_cmpxchg_fixup).
794 1: ldr r3, [r2] @ load current val
795 subs r3, r3, r0 @ compare with oldval
796 2: streq r1, [r2] @ store newval if eq
797 rsbs r0, r3, #0 @ set return val and C flag
802 @ Called from kuser_cmpxchg_check macro.
803 @ r2 = address of interrupted insn (must be preserved).
804 @ sp = saved regs. r7 and r8 are clobbered.
805 @ 1b = first critical insn, 2b = last critical insn.
806 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
808 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
810 rsbcss r8, r8, #(2b - 1b)
811 strcs r7, [sp, #S_PC]
816 #warning "NPTL on non MMU needs fixing"
825 mcr p15, 0, r0, c7, c10, 5 @ dmb
833 /* beware -- each __kuser slot must be 8 instructions max */
835 b __kuser_memory_barrier
845 * Reference prototype:
847 * int __kernel_get_tls(void)
851 * lr = return address
861 * Definition and user space usage example:
863 * typedef int (__kernel_get_tls_t)(void);
864 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
866 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
868 * This could be used as follows:
870 * #define __kernel_get_tls() \
871 * ({ register unsigned int __val asm("r0"); \
872 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
873 * : "=r" (__val) : : "lr","cc" ); \
877 __kuser_get_tls: @ 0xffff0fe0
879 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
880 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
882 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
887 .word 0 @ pad up to __kuser_helper_version
891 * Reference declaration:
893 * extern unsigned int __kernel_helper_version;
895 * Definition and user space usage example:
897 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
899 * User space may read this to determine the curent number of helpers
903 __kuser_helper_version: @ 0xffff0ffc
904 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
906 .globl __kuser_helper_end
913 * This code is copied to 0xffff0200 so we can use branches in the
914 * vectors, rather than ldr's. Note that this code must not
915 * exceed 0x300 bytes.
917 * Common stub entry macro:
918 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
920 * SP points to a minimal amount of processor-private memory, the address
921 * of which is copied into r0 for the mode specific abort handler.
923 .macro vector_stub, name, mode, correction=0
928 sub lr, lr, #\correction
932 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
935 stmia sp, {r0, lr} @ save r0, lr
937 str lr, [sp, #8] @ save spsr
940 @ Prepare for SVC32 mode. IRQs remain disabled.
943 eor r0, r0, #(\mode ^ SVC_MODE)
947 @ the branch table must immediately follow this code
951 ldr lr, [pc, lr, lsl #2]
952 movs pc, lr @ branch to handler in SVC mode
958 * Interrupt dispatcher
960 vector_stub irq, IRQ_MODE, 4
962 .long __irq_usr @ 0 (USR_26 / USR_32)
963 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
964 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
965 .long __irq_svc @ 3 (SVC_26 / SVC_32)
966 .long __irq_invalid @ 4
967 .long __irq_invalid @ 5
968 .long __irq_invalid @ 6
969 .long __irq_invalid @ 7
970 .long __irq_invalid @ 8
971 .long __irq_invalid @ 9
972 .long __irq_invalid @ a
973 .long __irq_invalid @ b
974 .long __irq_invalid @ c
975 .long __irq_invalid @ d
976 .long __irq_invalid @ e
977 .long __irq_invalid @ f
980 * Data abort dispatcher
981 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
983 vector_stub dabt, ABT_MODE, 8
985 .long __dabt_usr @ 0 (USR_26 / USR_32)
986 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
987 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
988 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
989 .long __dabt_invalid @ 4
990 .long __dabt_invalid @ 5
991 .long __dabt_invalid @ 6
992 .long __dabt_invalid @ 7
993 .long __dabt_invalid @ 8
994 .long __dabt_invalid @ 9
995 .long __dabt_invalid @ a
996 .long __dabt_invalid @ b
997 .long __dabt_invalid @ c
998 .long __dabt_invalid @ d
999 .long __dabt_invalid @ e
1000 .long __dabt_invalid @ f
1003 * Prefetch abort dispatcher
1004 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1006 vector_stub pabt, ABT_MODE, 4
1008 .long __pabt_usr @ 0 (USR_26 / USR_32)
1009 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1010 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1011 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1012 .long __pabt_invalid @ 4
1013 .long __pabt_invalid @ 5
1014 .long __pabt_invalid @ 6
1015 .long __pabt_invalid @ 7
1016 .long __pabt_invalid @ 8
1017 .long __pabt_invalid @ 9
1018 .long __pabt_invalid @ a
1019 .long __pabt_invalid @ b
1020 .long __pabt_invalid @ c
1021 .long __pabt_invalid @ d
1022 .long __pabt_invalid @ e
1023 .long __pabt_invalid @ f
1026 * Undef instr entry dispatcher
1027 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1029 vector_stub und, UND_MODE
1031 .long __und_usr @ 0 (USR_26 / USR_32)
1032 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1033 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1034 .long __und_svc @ 3 (SVC_26 / SVC_32)
1035 .long __und_invalid @ 4
1036 .long __und_invalid @ 5
1037 .long __und_invalid @ 6
1038 .long __und_invalid @ 7
1039 .long __und_invalid @ 8
1040 .long __und_invalid @ 9
1041 .long __und_invalid @ a
1042 .long __und_invalid @ b
1043 .long __und_invalid @ c
1044 .long __und_invalid @ d
1045 .long __und_invalid @ e
1046 .long __und_invalid @ f
1050 /*=============================================================================
1052 *-----------------------------------------------------------------------------
1053 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1054 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1055 * Basically to switch modes, we *HAVE* to clobber one register... brain
1056 * damage alert! I don't think that we can execute any code in here in any
1057 * other mode than FIQ... Ok you can switch to another mode, but you can't
1058 * get out of that mode without clobbering one register.
1064 /*=============================================================================
1065 * Address exception handler
1066 *-----------------------------------------------------------------------------
1067 * These aren't too critical.
1068 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1075 * We group all the following data together to optimise
1076 * for CPUs with separate I & D caches.
1086 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1088 .globl __vectors_start
1091 b vector_und + stubs_offset
1092 ldr pc, .LCvswi + stubs_offset
1093 b vector_pabt + stubs_offset
1094 b vector_dabt + stubs_offset
1095 b vector_addrexcptn + stubs_offset
1096 b vector_irq + stubs_offset
1097 b vector_fiq + stubs_offset
1099 .globl __vectors_end
1105 .globl cr_no_alignment
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