err.no Git - linux-2.6/blob - arch/arm/include/asm/hardware/dec21285.h

   1 /*
   2  *  arch/arm/include/asm/hardware/dec21285.h
   3  *
   4  *  Copyright (C) 1998 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  DC21285 registers
  11  */
  12 #define DC21285_PCI_IACK                0x79000000
  13 #define DC21285_ARMCSR_BASE             0x42000000
  14 #define DC21285_PCI_TYPE_0_CONFIG       0x7b000000
  15 #define DC21285_PCI_TYPE_1_CONFIG       0x7a000000
  16 #define DC21285_OUTBOUND_WRITE_FLUSH    0x78000000
  17 #define DC21285_FLASH                   0x41000000
  18 #define DC21285_PCI_IO                  0x7c000000
  19 #define DC21285_PCI_MEM                 0x80000000
  20
  21 #ifndef __ASSEMBLY__
  22 #include <asm/hardware.h>
  23 #define DC21285_IO(x)           ((volatile unsigned long *)(ARMCSR_BASE+(x)))
  24 #else
  25 #define DC21285_IO(x)           (x)
  26 #endif
  27
  28 #define CSR_PCICMD              DC21285_IO(0x0004)
  29 #define CSR_CLASSREV            DC21285_IO(0x0008)
  30 #define CSR_PCICACHELINESIZE    DC21285_IO(0x000c)
  31 #define CSR_PCICSRBASE          DC21285_IO(0x0010)
  32 #define CSR_PCICSRIOBASE        DC21285_IO(0x0014)
  33 #define CSR_PCISDRAMBASE        DC21285_IO(0x0018)
  34 #define CSR_PCIROMBASE          DC21285_IO(0x0030)
  35 #define CSR_MBOX0               DC21285_IO(0x0050)
  36 #define CSR_MBOX1               DC21285_IO(0x0054)
  37 #define CSR_MBOX2               DC21285_IO(0x0058)
  38 #define CSR_MBOX3               DC21285_IO(0x005c)
  39 #define CSR_DOORBELL            DC21285_IO(0x0060)
  40 #define CSR_DOORBELL_SETUP      DC21285_IO(0x0064)
  41 #define CSR_ROMWRITEREG         DC21285_IO(0x0068)
  42 #define CSR_CSRBASEMASK         DC21285_IO(0x00f8)
  43 #define CSR_CSRBASEOFFSET       DC21285_IO(0x00fc)
  44 #define CSR_SDRAMBASEMASK       DC21285_IO(0x0100)
  45 #define CSR_SDRAMBASEOFFSET     DC21285_IO(0x0104)
  46 #define CSR_ROMBASEMASK         DC21285_IO(0x0108)
  47 #define CSR_SDRAMTIMING         DC21285_IO(0x010c)
  48 #define CSR_SDRAMADDRSIZE0      DC21285_IO(0x0110)
  49 #define CSR_SDRAMADDRSIZE1      DC21285_IO(0x0114)
  50 #define CSR_SDRAMADDRSIZE2      DC21285_IO(0x0118)
  51 #define CSR_SDRAMADDRSIZE3      DC21285_IO(0x011c)
  52 #define CSR_I2O_INFREEHEAD      DC21285_IO(0x0120)
  53 #define CSR_I2O_INPOSTTAIL      DC21285_IO(0x0124)
  54 #define CSR_I2O_OUTPOSTHEAD     DC21285_IO(0x0128)
  55 #define CSR_I2O_OUTFREETAIL     DC21285_IO(0x012c)
  56 #define CSR_I2O_INFREECOUNT     DC21285_IO(0x0130)
  57 #define CSR_I2O_OUTPOSTCOUNT    DC21285_IO(0x0134)
  58 #define CSR_I2O_INPOSTCOUNT     DC21285_IO(0x0138)
  59 #define CSR_SA110_CNTL          DC21285_IO(0x013c)
  60 #define SA110_CNTL_INITCMPLETE          (1 << 0)
  61 #define SA110_CNTL_ASSERTSERR           (1 << 1)
  62 #define SA110_CNTL_RXSERR               (1 << 3)
  63 #define SA110_CNTL_SA110DRAMPARITY      (1 << 4)
  64 #define SA110_CNTL_PCISDRAMPARITY       (1 << 5)
  65 #define SA110_CNTL_DMASDRAMPARITY       (1 << 6)
  66 #define SA110_CNTL_DISCARDTIMER         (1 << 8)
  67 #define SA110_CNTL_PCINRESET            (1 << 9)
  68 #define SA110_CNTL_I2O_256              (0 << 10)
  69 #define SA110_CNTL_I20_512              (1 << 10)
  70 #define SA110_CNTL_I2O_1024             (2 << 10)
  71 #define SA110_CNTL_I2O_2048             (3 << 10)
  72 #define SA110_CNTL_I2O_4096             (4 << 10)
  73 #define SA110_CNTL_I2O_8192             (5 << 10)
  74 #define SA110_CNTL_I2O_16384            (6 << 10)
  75 #define SA110_CNTL_I2O_32768            (7 << 10)
  76 #define SA110_CNTL_WATCHDOG             (1 << 13)
  77 #define SA110_CNTL_ROMWIDTH_UNDEF       (0 << 14)
  78 #define SA110_CNTL_ROMWIDTH_16          (1 << 14)
  79 #define SA110_CNTL_ROMWIDTH_32          (2 << 14)
  80 #define SA110_CNTL_ROMWIDTH_8           (3 << 14)
  81 #define SA110_CNTL_ROMACCESSTIME(x)     ((x)<<16)
  82 #define SA110_CNTL_ROMBURSTTIME(x)      ((x)<<20)
  83 #define SA110_CNTL_ROMTRISTATETIME(x)   ((x)<<24)
  84 #define SA110_CNTL_XCSDIR(x)            ((x)<<28)
  85 #define SA110_CNTL_PCICFN               (1 << 31)
  86
  87 /*
  88  * footbridge_cfn_mode() is used when we want
  89  * to check whether we are the central function
  90  */
  91 #define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
  92 #if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
  93 #define footbridge_cfn_mode() __footbridge_cfn_mode()
  94 #elif defined(CONFIG_FOOTBRIDGE_HOST)
  95 #define footbridge_cfn_mode() (1)
  96 #else
  97 #define footbridge_cfn_mode() (0)
  98 #endif
  99
 100 #define CSR_PCIADDR_EXTN        DC21285_IO(0x0140)
 101 #define CSR_PREFETCHMEMRANGE    DC21285_IO(0x0144)
 102 #define CSR_XBUS_CYCLE          DC21285_IO(0x0148)
 103 #define CSR_XBUS_IOSTROBE       DC21285_IO(0x014c)
 104 #define CSR_DOORBELL_PCI        DC21285_IO(0x0150)
 105 #define CSR_DOORBELL_SA110      DC21285_IO(0x0154)
 106 #define CSR_UARTDR              DC21285_IO(0x0160)
 107 #define CSR_RXSTAT              DC21285_IO(0x0164)
 108 #define CSR_H_UBRLCR            DC21285_IO(0x0168)
 109 #define CSR_M_UBRLCR            DC21285_IO(0x016c)
 110 #define CSR_L_UBRLCR            DC21285_IO(0x0170)
 111 #define CSR_UARTCON             DC21285_IO(0x0174)
 112 #define CSR_UARTFLG             DC21285_IO(0x0178)
 113 #define CSR_IRQ_STATUS          DC21285_IO(0x0180)
 114 #define CSR_IRQ_RAWSTATUS       DC21285_IO(0x0184)
 115 #define CSR_IRQ_ENABLE          DC21285_IO(0x0188)
 116 #define CSR_IRQ_DISABLE         DC21285_IO(0x018c)
 117 #define CSR_IRQ_SOFT            DC21285_IO(0x0190)
 118 #define CSR_FIQ_STATUS          DC21285_IO(0x0280)
 119 #define CSR_FIQ_RAWSTATUS       DC21285_IO(0x0284)
 120 #define CSR_FIQ_ENABLE          DC21285_IO(0x0288)
 121 #define CSR_FIQ_DISABLE         DC21285_IO(0x028c)
 122 #define CSR_FIQ_SOFT            DC21285_IO(0x0290)
 123 #define CSR_TIMER1_LOAD         DC21285_IO(0x0300)
 124 #define CSR_TIMER1_VALUE        DC21285_IO(0x0304)
 125 #define CSR_TIMER1_CNTL         DC21285_IO(0x0308)
 126 #define CSR_TIMER1_CLR          DC21285_IO(0x030c)
 127 #define CSR_TIMER2_LOAD         DC21285_IO(0x0320)
 128 #define CSR_TIMER2_VALUE        DC21285_IO(0x0324)
 129 #define CSR_TIMER2_CNTL         DC21285_IO(0x0328)
 130 #define CSR_TIMER2_CLR          DC21285_IO(0x032c)
 131 #define CSR_TIMER3_LOAD         DC21285_IO(0x0340)
 132 #define CSR_TIMER3_VALUE        DC21285_IO(0x0344)
 133 #define CSR_TIMER3_CNTL         DC21285_IO(0x0348)
 134 #define CSR_TIMER3_CLR          DC21285_IO(0x034c)
 135 #define CSR_TIMER4_LOAD         DC21285_IO(0x0360)
 136 #define CSR_TIMER4_VALUE        DC21285_IO(0x0364)
 137 #define CSR_TIMER4_CNTL         DC21285_IO(0x0368)
 138 #define CSR_TIMER4_CLR          DC21285_IO(0x036c)
 139
 140 #define TIMER_CNTL_ENABLE       (1 << 7)
 141 #define TIMER_CNTL_AUTORELOAD   (1 << 6)
 142 #define TIMER_CNTL_DIV1         (0)
 143 #define TIMER_CNTL_DIV16        (1 << 2)
 144 #define TIMER_CNTL_DIV256       (2 << 2)
 145 #define TIMER_CNTL_CNTEXT       (3 << 2)
 146
 147