2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
21 #if defined(CONFIG_DEBUG_DC21285_PORT)
28 #elif defined(CONFIG_DEBUG_ICEDCC)
32 mcr p14, 0, \rb, c0, c1, 0
34 #elif defined(CONFIG_FOOTBRIDGE)
39 strb \rb, [r3, #0x3f8]
41 #elif defined(CONFIG_ARCH_RPC)
44 orr \rb, \rb, #0x00010000
47 strb \rb, [r3, #0x3f8 << 2]
49 #elif defined(CONFIG_ARCH_INTEGRATOR)
56 #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
59 orr \rb, \rb, #0x00100000
64 #elif defined(CONFIG_ARCH_SA1100)
66 mov \rb, #0x80000000 @ physical base address
67 # if defined(CONFIG_DEBUG_LL_SER3)
68 add \rb, \rb, #0x00050000 @ Ser3
70 add \rb, \rb, #0x00010000 @ Ser1
74 str \rb, [r3, #0x14] @ UTDR
76 #elif defined(CONFIG_ARCH_IXP4XX)
82 #elif defined(CONFIG_ARCH_IXP2000)
85 orr \rb, \rb, #0x00030000
90 #elif defined(CONFIG_ARCH_LH7A40X)
92 ldr \rb, =0x80000700 @ UART2 UARTBASE
97 #elif defined(CONFIG_ARCH_OMAP)
99 mov \rb, #0xff000000 @ physical base address
100 add \rb, \rb, #0x00fb0000
101 #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
102 add \rb, \rb, #0x00000800
104 #ifdef CONFIG_OMAP_LL_DEBUG_UART3
105 add \rb, \rb, #0x00009000
111 #elif defined(CONFIG_ARCH_IOP331)
114 orr \rb, \rb, #0x00ff0000
115 orr \rb, \rb, #0x0000f700 @ location of the UART
120 #elif defined(CONFIG_ARCH_S3C2410)
123 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
126 strb \rb, [r3, #0x20]
129 #error no serial architecture defined
144 .macro debug_reloc_start
147 kphex r6, 8 /* processor id */
149 kphex r7, 8 /* architecture id */
151 mrc p15, 0, r0, c1, c0
152 kphex r0, 8 /* control reg */
154 kphex r5, 8 /* decompressed kernel start */
156 kphex r8, 8 /* decompressed kernel end */
158 kphex r4, 8 /* kernel execution address */
163 .macro debug_reloc_end
165 kphex r5, 8 /* end of kernel */
168 bl memdump /* dump 256 bytes at start of kernel */
172 .section ".start", #alloc, #execinstr
174 * sort out different calling conventions
178 .type start,#function
184 .word 0x016f2818 @ Magic numbers to help the loader
185 .word start @ absolute load/run zImage address
186 .word _edata @ zImage end address
187 1: mov r7, r1 @ save architecture ID
190 #ifndef __ARM_ARCH_2__
192 * Booting from Angel - need to enter SVC mode and disable
193 * FIQs/IRQs (numeric definitions from angel arm.h source).
194 * We only do this if we were in user mode on entry.
196 mrs r2, cpsr @ get current mode
197 tst r2, #3 @ not user?
199 mov r0, #0x17 @ angel_SWIreason_EnterSVC
200 swi 0x123456 @ angel_SWI_ARM
202 mrs r2, cpsr @ turn off interrupts to
203 orr r2, r2, #0xc0 @ prevent angel from running
206 teqp pc, #0x0c000003 @ turn off interrupts
210 * Note that some cache flushing and other stuff may
211 * be needed here - is there an Angel SWI call for this?
215 * some architecture specific code can be inserted
216 * by the linker here, but it should preserve r7 and r8.
221 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
222 subs r0, r0, r1 @ calculate the delta offset
224 @ if delta is zero, we are
225 beq not_relocated @ running at the address we
229 * We're running at a different address. We need to fix
230 * up various pointers:
231 * r5 - zImage base address
239 #ifndef CONFIG_ZBOOT_ROM
241 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
242 * we need to fix up pointers into the BSS region.
252 * Relocate all entries in the GOT table.
254 1: ldr r1, [r6, #0] @ relocate entries in the GOT
255 add r1, r1, r0 @ table. This fixes up the
256 str r1, [r6], #4 @ C references.
262 * Relocate entries in the GOT table. We only relocate
263 * the entries that are outside the (relocated) BSS region.
265 1: ldr r1, [r6, #0] @ relocate entries in the GOT
266 cmp r1, r2 @ entry < bss_start ||
267 cmphs r3, r1 @ _end < entry
268 addlo r1, r1, r0 @ table. This fixes up the
269 str r1, [r6], #4 @ C references.
274 not_relocated: mov r0, #0
275 1: str r0, [r2], #4 @ clear bss
283 * The C runtime environment should now be setup
284 * sufficiently. Turn the cache on, set up some
285 * pointers, and start decompressing.
289 mov r1, sp @ malloc space above stack
290 add r2, sp, #0x10000 @ 64k max
293 * Check to see if we will overwrite ourselves.
294 * r4 = final kernel address
295 * r5 = start of this image
296 * r2 = end of malloc space (and therefore this image)
299 * r4 + image length <= r5 -> OK
303 add r0, r4, #4096*1024 @ 4MB largest kernel size
307 mov r5, r2 @ decompress after malloc space
313 bic r0, r0, #127 @ align the kernel length
315 * r0 = decompressed kernel length
317 * r4 = kernel execution address
318 * r5 = decompressed kernel start
320 * r7 = architecture ID
323 add r1, r5, r0 @ end of decompressed kernel
327 1: ldmia r2!, {r8 - r13} @ copy relocation code
328 stmia r1!, {r8 - r13}
329 ldmia r2!, {r8 - r13}
330 stmia r1!, {r8 - r13}
335 add pc, r5, r0 @ call relocation code
338 * We're not in danger of overwriting ourselves. Do this the simple way.
340 * r4 = kernel execution address
341 * r7 = architecture ID
343 wont_overwrite: mov r0, r4
350 .word __bss_start @ r2
354 .word _got_start @ r6
356 .word user_stack+4096 @ sp
357 LC1: .word reloc_end - reloc_start
360 #ifdef CONFIG_ARCH_RPC
362 params: ldr r0, =params_phys
369 * Turn on the cache. We need to setup some page tables so that we
370 * can have both the I and D caches on.
372 * We place the page tables 16k down from the kernel execution address,
373 * and we hope that nothing else is using it. If we're using it, we
377 * r4 = kernel execution address
379 * r7 = architecture number
380 * r8 = run-time address of "start"
382 * r1, r2, r3, r8, r9, r12 corrupted
383 * This routine must preserve:
387 cache_on: mov r3, #8 @ cache_on function
390 __setup_mmu: sub r3, r4, #16384 @ Page directory size
391 bic r3, r3, #0xff @ Align the pointer
394 * Initialise the page tables, turning on the cacheable and bufferable
395 * bits for the RAM area only.
399 mov r8, r8, lsl #18 @ start of RAM
400 add r9, r8, #0x10000000 @ a reasonable RAM size
404 1: cmp r1, r8 @ if virt > start of RAM
405 orrhs r1, r1, #0x0c @ set cacheable, bufferable
406 cmp r1, r9 @ if virt > end of RAM
407 bichs r1, r1, #0x0c @ clear cacheable, bufferable
408 str r1, [r0], #4 @ 1:1 mapping
413 * If ever we are running from Flash, then we surely want the cache
414 * to be enabled also for our execution instance... We map 2MB of it
415 * so there is no map overlap problem for up to 1 MB compressed kernel.
416 * If the execution is in RAM then we would only be duplicating the above.
421 orr r1, r1, r2, lsl #20
422 add r0, r3, r2, lsl #2
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
433 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
434 mrc p15, 0, r0, c1, c0, 0 @ read control reg
435 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
439 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
446 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
447 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
451 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
456 orr r0, r0, #0x000d @ Write buffer, mmu
459 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
460 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
461 mcr p15, 0, r0, c1, c0, 0 @ load control register
465 * All code following this line is relocatable. It is relocated by
466 * the above code to the end of the decompressed kernel image and
467 * executed there. During this time, we have no stacks.
469 * r0 = decompressed kernel length
471 * r4 = kernel execution address
472 * r5 = decompressed kernel start
474 * r7 = architecture ID
478 reloc_start: add r8, r5, r0
483 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
484 stmia r1!, {r0, r2, r3, r9 - r13}
491 call_kernel: bl cache_clean_flush
494 mov r1, r7 @ restore architecture number
495 mov pc, r4 @ call kernel
498 * Here follow the relocatable cache support functions for the
499 * various processors. This is a generic hook for locating an
500 * entry and jumping to an instruction at the specified offset
501 * from the start of the block. Please note this is all position
511 call_cache_fn: adr r12, proc_types
512 mrc p15, 0, r6, c0, c0 @ get processor ID
513 1: ldr r1, [r12, #0] @ get value
514 ldr r2, [r12, #4] @ get mask
515 eor r1, r1, r6 @ (real ^ match)
517 addeq pc, r12, r3 @ call cache function
522 * Table for cache operations. This is basically:
525 * - 'cache on' method instruction
526 * - 'cache off' method instruction
527 * - 'cache flush' method instruction
529 * We match an entry using: ((real_id ^ match) & mask) == 0
531 * Writethrough caches generally only need 'on' and 'off'
532 * methods. Writeback caches _must_ have the flush method
535 .type proc_types,#object
537 .word 0x41560600 @ ARM6/610
539 b __arm6_cache_off @ works, but slow
542 @ b __arm6_cache_on @ untested
544 @ b __armv3_cache_flush
546 .word 0x00000000 @ old ARM ID
552 .word 0x41007000 @ ARM7/710
558 .word 0x41807200 @ ARM720T (writethrough)
564 .word 0x00007000 @ ARM7 IDs
570 @ Everything from here on will be the new ID system.
572 .word 0x4401a100 @ sa110 / sa1100
576 b __armv4_cache_flush
578 .word 0x6901b110 @ sa1110
582 b __armv4_cache_flush
584 @ These match on the architecture ID
586 .word 0x00020000 @ ARMv4T
590 b __armv4_cache_flush
592 .word 0x00050000 @ ARMv5TE
596 b __armv4_cache_flush
598 .word 0x00060000 @ ARMv5TEJ
602 b __armv4_cache_flush
604 .word 0x00070000 @ ARMv6
608 b __armv6_cache_flush
610 .word 0 @ unrecognised type
616 .size proc_types, . - proc_types
619 * Turn off the Cache and MMU. ARMv3 does not support
620 * reading the control register, but ARMv4 does.
622 * On entry, r6 = processor ID
623 * On exit, r0, r1, r2, r3, r12 corrupted
624 * This routine must preserve: r4, r6, r7
627 cache_off: mov r3, #12 @ cache_off function
631 mrc p15, 0, r0, c1, c0
633 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
635 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
636 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
640 mov r0, #0x00000030 @ ARM6 control reg.
644 mov r0, #0x00000070 @ ARM7 control reg.
648 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
650 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
651 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
655 * Clean and flush the cache to maintain consistency.
660 * r1, r2, r3, r11, r12 corrupted
661 * This routine must preserve:
671 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
672 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
673 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
674 mcr p15, 0, r1, c7, c10, 4 @ drain WB
678 mov r2, #64*1024 @ default: 32K dcache size (*2)
679 mov r11, #32 @ default: 32 byte line size
680 mrc p15, 0, r3, c0, c0, 1 @ read cache type
681 teq r3, r6 @ cache ID register present?
686 mov r2, r2, lsl r1 @ base dcache size *2
687 tst r3, #1 << 14 @ test M bit
688 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
692 mov r11, r11, lsl r3 @ cache line size in bytes
694 bic r1, pc, #63 @ align to longest cache line
696 1: ldr r3, [r1], r11 @ s/w flush D cache
700 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
701 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
702 mcr p15, 0, r1, c7, c10, 4 @ drain WB
707 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
711 * Various debugging routines for printing hex characters and
712 * memory, which again must be relocatable.
715 .type phexbuf,#object
717 .size phexbuf, . - phexbuf
719 phex: adr r3, phexbuf
756 2: mov r0, r11, lsl #2
764 ldr r0, [r12, r11, lsl #2]
785 .section ".stack", "w"
786 user_stack: .space 4096