1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
15 1) Entry point for arch/powerpc
18 II - The DT block format
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
33 d) the /memory node(s)
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
45 b) Gianfar-compatible ethernet nodes
47 d) Interrupt controllers
49 f) Freescale SOC USB controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
64 VII - Marvell Discovery mv64[345]6x System Controller chips
65 1) The /system-controller node
66 2) Child nodes of /system-controller
67 a) Marvell Discovery MDIO bus
68 b) Marvell Discovery ethernet controller
69 c) Marvell Discovery PHY nodes
70 d) Marvell Discovery SDMA nodes
71 e) Marvell Discovery BRG nodes
72 f) Marvell Discovery CUNIT nodes
73 g) Marvell Discovery MPSCROUTING nodes
74 h) Marvell Discovery MPSCINTR nodes
75 i) Marvell Discovery MPSC nodes
76 j) Marvell Discovery Watch Dog Timer nodes
77 k) Marvell Discovery I2C nodes
78 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
79 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
80 n) Marvell Discovery GPP (General Purpose Pins) nodes
81 o) Marvell Discovery PCI host bridge node
82 p) Marvell Discovery CPU Error nodes
83 q) Marvell Discovery SRAM Controller nodes
84 r) Marvell Discovery PCI Error Handler nodes
85 s) Marvell Discovery Memory Controller nodes
87 VIII - Specifying interrupt information for devices
88 1) interrupts property
89 2) interrupt-parent property
90 3) OpenPIC Interrupt Controllers
91 4) ISA Interrupt Controllers
93 VIII - Specifying GPIO information for devices
95 2) gpio-controller nodes
97 Appendix A - Sample SOC node for MPC8540
103 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
105 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
106 clarifies the fact that a lot of things are
107 optional, the kernel only requires a very
108 small device tree, though it is encouraged
109 to provide an as complete one as possible.
111 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
113 - Define version 3 and new format version 16
114 for the DT block (version 16 needs kernel
115 patches, will be fwd separately).
116 String block now has a size, and full path
117 is replaced by unit name for more
119 linux,phandle is made optional, only nodes
120 that are referenced by other nodes need it.
121 "name" property is now automatically
122 deduced from the unit name
124 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
125 OF_DT_END_NODE in structure definition.
126 - Change version 16 format to always align
127 property data to 4 bytes. Since tokens are
128 already aligned, that means no specific
129 required alignment between property size
130 and property data. The old style variable
131 alignment would make it impossible to do
132 "simple" insertion of properties using
133 memmove (thanks Milton for
134 noticing). Updated kernel patch as well
135 - Correct a few more alignment constraints
136 - Add a chapter about the device-tree
137 compiler and the textural representation of
138 the tree that can be "compiled" by dtc.
140 November 21, 2005: Rev 0.5
141 - Additions/generalizations for 32-bit
142 - Changed to reflect the new arch/powerpc
148 - Add some definitions of interrupt tree (simple/complex)
149 - Add some definitions for PCI host bridges
150 - Add some common address format examples
151 - Add definitions for standard properties and "compatible"
152 names for cells that are not already defined by the existing
154 - Compare FSL SOC use of PCI to standard and make sure no new
155 node definition required.
156 - Add more information about node definitions for SOC devices
157 that currently have no standard, like the FSL CPM.
163 During the recent development of the Linux/ppc64 kernel, and more
164 specifically, the addition of new platform types outside of the old
165 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
166 regarding the kernel entry and bootloader <-> kernel interfaces, in
167 order to avoid the degeneration that had become the ppc32 kernel entry
168 point and the way a new platform should be added to the kernel. The
169 legacy iSeries platform breaks those rules as it predates this scheme,
170 but no new board support will be accepted in the main tree that
171 doesn't follows them properly. In addition, since the advent of the
172 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
173 platforms and 32-bit platforms which move into arch/powerpc will be
174 required to use these rules as well.
176 The main requirement that will be defined in more detail below is
177 the presence of a device-tree whose format is defined after Open
178 Firmware specification. However, in order to make life easier
179 to embedded board vendors, the kernel doesn't require the device-tree
180 to represent every device in the system and only requires some nodes
181 and properties to be present. This will be described in detail in
182 section III, but, for example, the kernel does not require you to
183 create a node for every PCI device in the system. It is a requirement
184 to have a node for PCI host bridges in order to provide interrupt
185 routing informations and memory/IO ranges, among others. It is also
186 recommended to define nodes for on chip devices and other busses that
187 don't specifically fit in an existing OF specification. This creates a
188 great flexibility in the way the kernel can then probe those and match
189 drivers to device, without having to hard code all sorts of tables. It
190 also makes it more flexible for board vendors to do minor hardware
191 upgrades without significantly impacting the kernel code or cluttering
192 it with special cases.
195 1) Entry point for arch/powerpc
196 -------------------------------
198 There is one and one single entry point to the kernel, at the start
199 of the kernel image. That entry point supports two calling
202 a) Boot from Open Firmware. If your firmware is compatible
203 with Open Firmware (IEEE 1275) or provides an OF compatible
204 client interface API (support for "interpret" callback of
205 forth words isn't required), you can enter the kernel with:
207 r5 : OF callback pointer as defined by IEEE 1275
208 bindings to powerpc. Only the 32-bit client interface
209 is currently supported
211 r3, r4 : address & length of an initrd if any or 0
213 The MMU is either on or off; the kernel will run the
214 trampoline located in arch/powerpc/kernel/prom_init.c to
215 extract the device-tree and other information from open
216 firmware and build a flattened device-tree as described
217 in b). prom_init() will then re-enter the kernel using
218 the second method. This trampoline code runs in the
219 context of the firmware, which is supposed to handle all
220 exceptions during that time.
222 b) Direct entry with a flattened device-tree block. This entry
223 point is called by a) after the OF trampoline and can also be
224 called directly by a bootloader that does not support the Open
225 Firmware client interface. It is also used by "kexec" to
226 implement "hot" booting of a new kernel from a previous
227 running one. This method is what I will describe in more
228 details in this document, as method a) is simply standard Open
229 Firmware, and thus should be implemented according to the
230 various standard documents defining it and its binding to the
231 PowerPC platform. The entry point definition then becomes:
233 r3 : physical pointer to the device-tree block
234 (defined in chapter II) in RAM
236 r4 : physical pointer to the kernel itself. This is
237 used by the assembly code to properly disable the MMU
238 in case you are entering the kernel with MMU enabled
239 and a non-1:1 mapping.
241 r5 : NULL (as to differentiate with method a)
243 Note about SMP entry: Either your firmware puts your other
244 CPUs in some sleep loop or spin loop in ROM where you can get
245 them out via a soft reset or some other means, in which case
246 you don't need to care, or you'll have to enter the kernel
247 with all CPUs. The way to do that with method b) will be
248 described in a later revision of this document.
256 Board supports (platforms) are not exclusive config options. An
257 arbitrary set of board supports can be built in a single kernel
258 image. The kernel will "know" what set of functions to use for a
259 given platform based on the content of the device-tree. Thus, you
262 a) add your platform support as a _boolean_ option in
263 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
264 PPC_PMAC and PPC_MAPLE. The later is probably a good
265 example of a board support to start from.
267 b) create your main platform file as
268 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
269 to the Makefile under the condition of your CONFIG_
270 option. This file will define a structure of type "ppc_md"
271 containing the various callbacks that the generic code will
272 use to get to your platform specific code
274 c) Add a reference to your "ppc_md" structure in the
275 "machines" table in arch/powerpc/kernel/setup_64.c if you are
278 d) request and get assigned a platform number (see PLATFORM_*
279 constants in include/asm-powerpc/processor.h
281 32-bit embedded kernels:
283 Currently, board support is essentially an exclusive config option.
284 The kernel is configured for a single platform. Part of the reason
285 for this is to keep kernels on embedded systems small and efficient;
286 part of this is due to the fact the code is already that way. In the
287 future, a kernel may support multiple platforms, but only if the
288 platforms feature the same core architecture. A single kernel build
289 cannot support both configurations with Book E and configurations
290 with classic Powerpc architectures.
292 32-bit embedded platforms that are moved into arch/powerpc using a
293 flattened device tree should adopt the merged tree practice of
294 setting ppc_md up dynamically, even though the kernel is currently
295 built with support for only a single platform at a time. This allows
296 unification of the setup code, and will make it easier to go to a
297 multiple-platform-support model in the future.
299 NOTE: I believe the above will be true once Ben's done with the merge
300 of the boot sequences.... someone speak up if this is wrong!
302 To add a 32-bit embedded platform support, follow the instructions
303 for 64-bit platforms above, with the exception that the Kconfig
304 option should be set up such that the kernel builds exclusively for
305 the platform selected. The processor type for the platform should
306 enable another config option to select the specific board
309 NOTE: If Ben doesn't merge the setup files, may need to change this to
313 I will describe later the boot process and various callbacks that
314 your platform should implement.
317 II - The DT block format
318 ========================
321 This chapter defines the actual format of the flattened device-tree
322 passed to the kernel. The actual content of it and kernel requirements
323 are described later. You can find example of code manipulating that
324 format in various places, including arch/powerpc/kernel/prom_init.c
325 which will generate a flattened device-tree from the Open Firmware
326 representation, or the fs2dt utility which is part of the kexec tools
327 which will generate one from a filesystem representation. It is
328 expected that a bootloader like uboot provides a bit more support,
329 that will be discussed later as well.
331 Note: The block has to be in main memory. It has to be accessible in
332 both real mode and virtual mode with no mapping other than main
333 memory. If you are writing a simple flash bootloader, it should copy
334 the block to RAM before passing it to the kernel.
340 The kernel is entered with r3 pointing to an area of memory that is
341 roughly described in include/asm-powerpc/prom.h by the structure
344 struct boot_param_header {
345 u32 magic; /* magic word OF_DT_HEADER */
346 u32 totalsize; /* total size of DT block */
347 u32 off_dt_struct; /* offset to structure */
348 u32 off_dt_strings; /* offset to strings */
349 u32 off_mem_rsvmap; /* offset to memory reserve map
351 u32 version; /* format version */
352 u32 last_comp_version; /* last compatible version */
354 /* version 2 fields below */
355 u32 boot_cpuid_phys; /* Which physical CPU id we're
357 /* version 3 fields below */
358 u32 size_dt_strings; /* size of the strings block */
360 /* version 17 fields below */
361 u32 size_dt_struct; /* size of the DT structure block */
364 Along with the constants:
366 /* Definitions used by the flattened device tree */
367 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
369 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
371 #define OF_DT_END_NODE 0x2 /* End node */
372 #define OF_DT_PROP 0x3 /* Property: name off,
374 #define OF_DT_END 0x9
376 All values in this header are in big endian format, the various
377 fields in this header are defined more precisely below. All
378 "offset" values are in bytes from the start of the header; that is
379 from the value of r3.
383 This is a magic value that "marks" the beginning of the
384 device-tree block header. It contains the value 0xd00dfeed and is
385 defined by the constant OF_DT_HEADER
389 This is the total size of the DT block including the header. The
390 "DT" block should enclose all data structures defined in this
391 chapter (who are pointed to by offsets in this header). That is,
392 the device-tree structure, strings, and the memory reserve map.
396 This is an offset from the beginning of the header to the start
397 of the "structure" part the device tree. (see 2) device tree)
401 This is an offset from the beginning of the header to the start
402 of the "strings" part of the device-tree
406 This is an offset from the beginning of the header to the start
407 of the reserved memory map. This map is a list of pairs of 64-
408 bit integers. Each pair is a physical address and a size. The
409 list is terminated by an entry of size 0. This map provides the
410 kernel with a list of physical memory areas that are "reserved"
411 and thus not to be used for memory allocations, especially during
412 early initialization. The kernel needs to allocate memory during
413 boot for things like un-flattening the device-tree, allocating an
414 MMU hash table, etc... Those allocations must be done in such a
415 way to avoid overriding critical things like, on Open Firmware
416 capable machines, the RTAS instance, or on some pSeries, the TCE
417 tables used for the iommu. Typically, the reserve map should
418 contain _at least_ this DT block itself (header,total_size). If
419 you are passing an initrd to the kernel, you should reserve it as
420 well. You do not need to reserve the kernel image itself. The map
421 should be 64-bit aligned.
425 This is the version of this structure. Version 1 stops
426 here. Version 2 adds an additional field boot_cpuid_phys.
427 Version 3 adds the size of the strings block, allowing the kernel
428 to reallocate it easily at boot and free up the unused flattened
429 structure after expansion. Version 16 introduces a new more
430 "compact" format for the tree itself that is however not backward
431 compatible. Version 17 adds an additional field, size_dt_struct,
432 allowing it to be reallocated or moved more easily (this is
433 particularly useful for bootloaders which need to make
434 adjustments to a device tree based on probed information). You
435 should always generate a structure of the highest version defined
436 at the time of your implementation. Currently that is version 17,
437 unless you explicitly aim at being backward compatible.
441 Last compatible version. This indicates down to what version of
442 the DT block you are backward compatible. For example, version 2
443 is backward compatible with version 1 (that is, a kernel build
444 for version 1 will be able to boot with a version 2 format). You
445 should put a 1 in this field if you generate a device tree of
446 version 1 to 3, or 16 if you generate a tree of version 16 or 17
447 using the new unit name format.
451 This field only exist on version 2 headers. It indicate which
452 physical CPU ID is calling the kernel entry point. This is used,
453 among others, by kexec. If you are on an SMP system, this value
454 should match the content of the "reg" property of the CPU node in
455 the device-tree corresponding to the CPU calling the kernel entry
456 point (see further chapters for more informations on the required
457 device-tree contents)
461 This field only exists on version 3 and later headers. It
462 gives the size of the "strings" section of the device tree (which
463 starts at the offset given by off_dt_strings).
467 This field only exists on version 17 and later headers. It gives
468 the size of the "structure" section of the device tree (which
469 starts at the offset given by off_dt_struct).
471 So the typical layout of a DT block (though the various parts don't
472 need to be in that order) looks like this (addresses go from top to
476 ------------------------------
477 r3 -> | struct boot_param_header |
478 ------------------------------
479 | (alignment gap) (*) |
480 ------------------------------
481 | memory reserve map |
482 ------------------------------
484 ------------------------------
486 | device-tree structure |
488 ------------------------------
490 ------------------------------
492 | device-tree strings |
494 -----> ------------------------------
499 (*) The alignment gaps are not necessarily present; their presence
500 and size are dependent on the various alignment requirements of
501 the individual data blocks.
504 2) Device tree generalities
505 ---------------------------
507 This device-tree itself is separated in two different blocks, a
508 structure block and a strings block. Both need to be aligned to a 4
511 First, let's quickly describe the device-tree concept before detailing
512 the storage format. This chapter does _not_ describe the detail of the
513 required types of nodes & properties for the kernel, this is done
514 later in chapter III.
516 The device-tree layout is strongly inherited from the definition of
517 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
518 nodes, each node having two or more named properties. A property can
521 It is a tree, so each node has one and only one parent except for the
522 root node who has no parent.
524 A node has 2 names. The actual node name is generally contained in a
525 property of type "name" in the node property list whose value is a
526 zero terminated string and is mandatory for version 1 to 3 of the
527 format definition (as it is in Open Firmware). Version 16 makes it
528 optional as it can generate it from the unit name defined below.
530 There is also a "unit name" that is used to differentiate nodes with
531 the same name at the same level, it is usually made of the node
532 names, the "@" sign, and a "unit address", which definition is
533 specific to the bus type the node sits on.
535 The unit name doesn't exist as a property per-se but is included in
536 the device-tree structure. It is typically used to represent "path" in
537 the device-tree. More details about the actual format of these will be
540 The kernel powerpc generic code does not make any formal use of the
541 unit address (though some board support code may do) so the only real
542 requirement here for the unit address is to ensure uniqueness of
543 the node unit name at a given level of the tree. Nodes with no notion
544 of address and no possible sibling of the same name (like /memory or
545 /cpus) may omit the unit address in the context of this specification,
546 or use the "@0" default unit address. The unit name is used to define
547 a node "full path", which is the concatenation of all parent node
548 unit names separated with "/".
550 The root node doesn't have a defined name, and isn't required to have
551 a name property either if you are using version 3 or earlier of the
552 format. It also has no unit address (no @ symbol followed by a unit
553 address). The root node unit name is thus an empty string. The full
554 path to the root node is "/".
556 Every node which actually represents an actual device (that is, a node
557 which isn't only a virtual "container" for more nodes, like "/cpus"
558 is) is also required to have a "device_type" property indicating the
561 Finally, every node that can be referenced from a property in another
562 node is required to have a "linux,phandle" property. Real open
563 firmware implementations provide a unique "phandle" value for every
564 node that the "prom_init()" trampoline code turns into
565 "linux,phandle" properties. However, this is made optional if the
566 flattened device tree is used directly. An example of a node
567 referencing another node via "phandle" is when laying out the
568 interrupt tree which will be described in a further version of this
571 This "linux, phandle" property is a 32-bit value that uniquely
572 identifies a node. You are free to use whatever values or system of
573 values, internal pointers, or whatever to generate these, the only
574 requirement is that every node for which you provide that property has
575 a unique value for it.
577 Here is an example of a simple device-tree. In this example, an "o"
578 designates a node followed by the node unit name. Properties are
579 presented with their name followed by their content. "content"
580 represents an ASCII string (zero terminated) value, while <content>
581 represents a 32-bit hexadecimal value. The various nodes in this
582 example will be discussed in a later chapter. At this point, it is
583 only meant to give you a idea of what a device-tree looks like. I have
584 purposefully kept the "name" and "linux,phandle" properties which
585 aren't necessary in order to give you a better idea of what the tree
586 looks like in practice.
589 |- name = "device-tree"
590 |- model = "MyBoardName"
591 |- compatible = "MyBoardFamilyName"
592 |- #address-cells = <2>
594 |- linux,phandle = <0>
598 | | - linux,phandle = <1>
599 | | - #address-cells = <1>
600 | | - #size-cells = <0>
603 | |- name = "PowerPC,970"
604 | |- device_type = "cpu"
606 | |- clock-frequency = <5f5e1000>
608 | |- linux,phandle = <2>
612 | |- device_type = "memory"
613 | |- reg = <00000000 00000000 00000000 20000000>
614 | |- linux,phandle = <3>
618 |- bootargs = "root=/dev/sda2"
619 |- linux,phandle = <4>
621 This tree is almost a minimal tree. It pretty much contains the
622 minimal set of required nodes and properties to boot a linux kernel;
623 that is, some basic model informations at the root, the CPUs, and the
624 physical memory layout. It also includes misc information passed
625 through /chosen, like in this example, the platform type (mandatory)
626 and the kernel command line arguments (optional).
628 The /cpus/PowerPC,970@0/64-bit property is an example of a
629 property without a value. All other properties have a value. The
630 significance of the #address-cells and #size-cells properties will be
631 explained in chapter IV which defines precisely the required nodes and
632 properties and their content.
635 3) Device tree "structure" block
637 The structure of the device tree is a linearized tree structure. The
638 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
639 ends that node definition. Child nodes are simply defined before
640 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
641 bit value. The tree has to be "finished" with a OF_DT_END token
643 Here's the basic structure of a single node:
645 * token OF_DT_BEGIN_NODE (that is 0x00000001)
646 * for version 1 to 3, this is the node full path as a zero
647 terminated string, starting with "/". For version 16 and later,
648 this is the node unit name only (or an empty string for the
650 * [align gap to next 4 bytes boundary]
652 * token OF_DT_PROP (that is 0x00000003)
653 * 32-bit value of property value size in bytes (or 0 if no
655 * 32-bit value of offset in string block of property name
656 * property value data if any
657 * [align gap to next 4 bytes boundary]
658 * [child nodes if any]
659 * token OF_DT_END_NODE (that is 0x00000002)
661 So the node content can be summarized as a start token, a full path,
662 a list of properties, a list of child nodes, and an end token. Every
663 child node is a full node structure itself as defined above.
665 NOTE: The above definition requires that all property definitions for
666 a particular node MUST precede any subnode definitions for that node.
667 Although the structure would not be ambiguous if properties and
668 subnodes were intermingled, the kernel parser requires that the
669 properties come first (up until at least 2.6.22). Any tools
670 manipulating a flattened tree must take care to preserve this
673 4) Device tree "strings" block
675 In order to save space, property names, which are generally redundant,
676 are stored separately in the "strings" block. This block is simply the
677 whole bunch of zero terminated strings for all property names
678 concatenated together. The device-tree property definitions in the
679 structure block will contain offset values from the beginning of the
683 III - Required content of the device tree
684 =========================================
686 WARNING: All "linux,*" properties defined in this document apply only
687 to a flattened device-tree. If your platform uses a real
688 implementation of Open Firmware or an implementation compatible with
689 the Open Firmware client interface, those properties will be created
690 by the trampoline code in the kernel's prom_init() file. For example,
691 that's where you'll have to add code to detect your board model and
692 set the platform number. However, when using the flattened device-tree
693 entry point, there is no prom_init() pass, and thus you have to
694 provide those properties yourself.
697 1) Note about cells and address representation
698 ----------------------------------------------
700 The general rule is documented in the various Open Firmware
701 documentations. If you choose to describe a bus with the device-tree
702 and there exist an OF bus binding, then you should follow the
703 specification. However, the kernel does not require every single
704 device or bus to be described by the device tree.
706 In general, the format of an address for a device is defined by the
707 parent bus type, based on the #address-cells and #size-cells
708 properties. Note that the parent's parent definitions of #address-cells
709 and #size-cells are not inhereted so every node with children must specify
710 them. The kernel requires the root node to have those properties defining
711 addresses format for devices directly mapped on the processor bus.
713 Those 2 properties define 'cells' for representing an address and a
714 size. A "cell" is a 32-bit number. For example, if both contain 2
715 like the example tree given above, then an address and a size are both
716 composed of 2 cells, and each is a 64-bit number (cells are
717 concatenated and expected to be in big endian format). Another example
718 is the way Apple firmware defines them, with 2 cells for an address
719 and one cell for a size. Most 32-bit implementations should define
720 #address-cells and #size-cells to 1, which represents a 32-bit value.
721 Some 32-bit processors allow for physical addresses greater than 32
722 bits; these processors should define #address-cells as 2.
724 "reg" properties are always a tuple of the type "address size" where
725 the number of cells of address and size is specified by the bus
726 #address-cells and #size-cells. When a bus supports various address
727 spaces and other flags relative to a given address allocation (like
728 prefetchable, etc...) those flags are usually added to the top level
729 bits of the physical address. For example, a PCI physical address is
730 made of 3 cells, the bottom two containing the actual address itself
731 while the top cell contains address space indication, flags, and pci
732 bus & device numbers.
734 For busses that support dynamic allocation, it's the accepted practice
735 to then not provide the address in "reg" (keep it 0) though while
736 providing a flag indicating the address is dynamically allocated, and
737 then, to provide a separate "assigned-addresses" property that
738 contains the fully allocated addresses. See the PCI OF bindings for
741 In general, a simple bus with no address space bits and no dynamic
742 allocation is preferred if it reflects your hardware, as the existing
743 kernel address parsing functions will work out of the box. If you
744 define a bus type with a more complex address format, including things
745 like address space bits, you'll have to add a bus translator to the
746 prom_parse.c file of the recent kernels for your bus type.
748 The "reg" property only defines addresses and sizes (if #size-cells is
749 non-0) within a given bus. In order to translate addresses upward
750 (that is into parent bus addresses, and possibly into CPU physical
751 addresses), all busses must contain a "ranges" property. If the
752 "ranges" property is missing at a given level, it's assumed that
753 translation isn't possible, i.e., the registers are not visible on the
754 parent bus. The format of the "ranges" property for a bus is a list
757 bus address, parent bus address, size
759 "bus address" is in the format of the bus this bus node is defining,
760 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
761 address, size) defines a range of addresses for child devices. "parent
762 bus address" is in the format of the parent bus of this bus. For
763 example, for a PCI host controller, that would be a CPU address. For a
764 PCI<->ISA bridge, that would be a PCI address. It defines the base
765 address in the parent bus where the beginning of that range is mapped.
767 For a new 64-bit powerpc board, I recommend either the 2/2 format or
768 Apple's 2/1 format which is slightly more compact since sizes usually
769 fit in a single 32-bit word. New 32-bit powerpc boards should use a
770 1/1 format, unless the processor supports physical addresses greater
771 than 32-bits, in which case a 2/1 format is recommended.
773 Alternatively, the "ranges" property may be empty, indicating that the
774 registers are visible on the parent bus using an identity mapping
775 translation. In other words, the parent bus address space is the same
776 as the child bus address space.
778 2) Note about "compatible" properties
779 -------------------------------------
781 These properties are optional, but recommended in devices and the root
782 node. The format of a "compatible" property is a list of concatenated
783 zero terminated strings. They allow a device to express its
784 compatibility with a family of similar devices, in some cases,
785 allowing a single driver to match against several devices regardless
786 of their actual names.
788 3) Note about "name" properties
789 -------------------------------
791 While earlier users of Open Firmware like OldWorld macintoshes tended
792 to use the actual device name for the "name" property, it's nowadays
793 considered a good practice to use a name that is closer to the device
794 class (often equal to device_type). For example, nowadays, ethernet
795 controllers are named "ethernet", an additional "model" property
796 defining precisely the chip type/model, and "compatible" property
797 defining the family in case a single driver can driver more than one
798 of these chips. However, the kernel doesn't generally put any
799 restriction on the "name" property; it is simply considered good
800 practice to follow the standard and its evolutions as closely as
803 Note also that the new format version 16 makes the "name" property
804 optional. If it's absent for a node, then the node's unit name is then
805 used to reconstruct the name. That is, the part of the unit name
806 before the "@" sign is used (or the entire unit name if no "@" sign
809 4) Note about node and property names and character set
810 -------------------------------------------------------
812 While open firmware provides more flexible usage of 8859-1, this
813 specification enforces more strict rules. Nodes and properties should
814 be comprised only of ASCII characters 'a' to 'z', '0' to
815 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
816 allow uppercase characters 'A' to 'Z' (property names should be
817 lowercase. The fact that vendors like Apple don't respect this rule is
818 irrelevant here). Additionally, node and property names should always
819 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
822 The maximum number of characters for both nodes and property names
823 is 31. In the case of node names, this is only the leftmost part of
824 a unit name (the pure "name" property), it doesn't include the unit
825 address which can extend beyond that limit.
828 5) Required nodes and properties
829 --------------------------------
830 These are all that are currently required. However, it is strongly
831 recommended that you expose PCI host bridges as documented in the
832 PCI binding to open firmware, and your interrupt tree as documented
833 in OF interrupt tree specification.
837 The root node requires some properties to be present:
839 - model : this is your board name/model
840 - #address-cells : address representation for "root" devices
841 - #size-cells: the size representation for "root" devices
842 - device_type : This property shouldn't be necessary. However, if
843 you decide to create a device_type for your root node, make sure it
844 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
845 one for 64-bit, or a CHRP-type machine for 32-bit as this will
846 matched by the kernel this way.
848 Additionally, some recommended properties are:
850 - compatible : the board "family" generally finds its way here,
851 for example, if you have 2 board models with a similar layout,
852 that typically get driven by the same platform code in the
853 kernel, you would use a different "model" property but put a
854 value in "compatible". The kernel doesn't directly use that
855 value but it is generally useful.
857 The root node is also generally where you add additional properties
858 specific to your board like the serial number if any, that sort of
859 thing. It is recommended that if you add any "custom" property whose
860 name may clash with standard defined ones, you prefix them with your
861 vendor name and a comma.
865 This node is the parent of all individual CPU nodes. It doesn't
866 have any specific requirements, though it's generally good practice
869 #address-cells = <00000001>
870 #size-cells = <00000000>
872 This defines that the "address" for a CPU is a single cell, and has
873 no meaningful size. This is not necessary but the kernel will assume
874 that format when reading the "reg" properties of a CPU node, see
879 So under /cpus, you are supposed to create a node for every CPU on
880 the machine. There is no specific restriction on the name of the
881 CPU, though It's common practice to call it PowerPC,<name>. For
882 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
886 - device_type : has to be "cpu"
887 - reg : This is the physical CPU number, it's a single 32-bit cell
888 and is also used as-is as the unit number for constructing the
889 unit name in the full path. For example, with 2 CPUs, you would
891 /cpus/PowerPC,970FX@0
892 /cpus/PowerPC,970FX@1
893 (unit addresses do not require leading zeroes)
894 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
895 - i-cache-block-size : one cell, L1 instruction cache block size in
897 - d-cache-size : one cell, size of L1 data cache in bytes
898 - i-cache-size : one cell, size of L1 instruction cache in bytes
900 (*) The cache "block" size is the size on which the cache management
901 instructions operate. Historically, this document used the cache
902 "line" size here which is incorrect. The kernel will prefer the cache
903 block size and will fallback to cache line size for backward
906 Recommended properties:
908 - timebase-frequency : a cell indicating the frequency of the
909 timebase in Hz. This is not directly used by the generic code,
910 but you are welcome to copy/paste the pSeries code for setting
911 the kernel timebase/decrementer calibration based on this
913 - clock-frequency : a cell indicating the CPU core clock frequency
914 in Hz. A new property will be defined for 64-bit values, but if
915 your frequency is < 4Ghz, one cell is enough. Here as well as
916 for the above, the common code doesn't use that property, but
917 you are welcome to re-use the pSeries or Maple one. A future
918 kernel version might provide a common function for this.
919 - d-cache-line-size : one cell, L1 data cache line size in bytes
920 if different from the block size
921 - i-cache-line-size : one cell, L1 instruction cache line size in
922 bytes if different from the block size
924 You are welcome to add any property you find relevant to your board,
925 like some information about the mechanism used to soft-reset the
926 CPUs. For example, Apple puts the GPIO number for CPU soft reset
927 lines in there as a "soft-reset" property since they start secondary
928 CPUs by soft-resetting them.
931 d) the /memory node(s)
933 To define the physical memory layout of your board, you should
934 create one or more memory node(s). You can either create a single
935 node with all memory ranges in its reg property, or you can create
936 several nodes, as you wish. The unit address (@ part) used for the
937 full path is the address of the first range of memory defined by a
938 given node. If you use a single memory node, this will typically be
943 - device_type : has to be "memory"
944 - reg : This property contains all the physical memory ranges of
945 your board. It's a list of addresses/sizes concatenated
946 together, with the number of cells of each defined by the
947 #address-cells and #size-cells of the root node. For example,
948 with both of these properties being 2 like in the example given
949 earlier, a 970 based machine with 6Gb of RAM could typically
950 have a "reg" property here that looks like:
952 00000000 00000000 00000000 80000000
953 00000001 00000000 00000001 00000000
955 That is a range starting at 0 of 0x80000000 bytes and a range
956 starting at 0x100000000 and of 0x100000000 bytes. You can see
957 that there is no memory covering the IO hole between 2Gb and
958 4Gb. Some vendors prefer splitting those ranges into smaller
959 segments, but the kernel doesn't care.
963 This node is a bit "special". Normally, that's where open firmware
964 puts some variable environment information, like the arguments, or
965 the default input/output devices.
967 This specification makes a few of these mandatory, but also defines
968 some linux-specific properties that would be normally constructed by
969 the prom_init() trampoline when booting with an OF client interface,
970 but that you have to provide yourself when using the flattened format.
972 Recommended properties:
974 - bootargs : This zero-terminated string is passed as the kernel
976 - linux,stdout-path : This is the full path to your standard
977 console device if any. Typically, if you have serial devices on
978 your board, you may want to put the full path to the one set as
979 the default console in the firmware here, for the kernel to pick
980 it up as its own default console. If you look at the function
981 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
982 that the kernel tries to find out the default console and has
983 knowledge of various types like 8250 serial ports. You may want
984 to extend this function to add your own.
986 Note that u-boot creates and fills in the chosen node for platforms
989 (Note: a practice that is now obsolete was to include a property
990 under /chosen called interrupt-controller which had a phandle value
991 that pointed to the main interrupt controller)
993 f) the /soc<SOCname> node
995 This node is used to represent a system-on-a-chip (SOC) and must be
996 present if the processor is a SOC. The top-level soc node contains
997 information that is global to all devices on the SOC. The node name
998 should contain a unit address for the SOC, which is the base address
999 of the memory-mapped register set for the SOC. The name of an soc
1000 node should start with "soc", and the remainder of the name should
1001 represent the part number for the soc. For example, the MPC8540's
1002 soc node would be called "soc8540".
1004 Required properties:
1006 - device_type : Should be "soc"
1007 - ranges : Should be defined as specified in 1) to describe the
1008 translation of SOC addresses for memory mapped SOC registers.
1009 - bus-frequency: Contains the bus frequency for the SOC node.
1010 Typically, the value of this field is filled in by the boot
1014 Recommended properties:
1016 - reg : This property defines the address and size of the
1017 memory-mapped registers that are used for the SOC node itself.
1018 It does not include the child device registers - these will be
1019 defined inside each child node. The address specified in the
1020 "reg" property should match the unit address of the SOC node.
1021 - #address-cells : Address representation for "soc" devices. The
1022 format of this field may vary depending on whether or not the
1023 device registers are memory mapped. For memory mapped
1024 registers, this field represents the number of cells needed to
1025 represent the address of the registers. For SOCs that do not
1026 use MMIO, a special address format should be defined that
1027 contains enough cells to represent the required information.
1028 See 1) above for more details on defining #address-cells.
1029 - #size-cells : Size representation for "soc" devices
1030 - #interrupt-cells : Defines the width of cells used to represent
1031 interrupts. Typically this value is <2>, which includes a
1032 32-bit number that represents the interrupt number, and a
1033 32-bit number that represents the interrupt sense and level.
1034 This field is only needed if the SOC contains an interrupt
1037 The SOC node may contain child nodes for each SOC device that the
1038 platform uses. Nodes should not be created for devices which exist
1039 on the SOC but are not used by a particular platform. See chapter VI
1040 for more information on how to specify devices that are part of a SOC.
1042 Example SOC node for the MPC8540:
1045 #address-cells = <1>;
1047 #interrupt-cells = <2>;
1048 device_type = "soc";
1049 ranges = <00000000 e0000000 00100000>
1050 reg = <e0000000 00003000>;
1051 bus-frequency = <0>;
1056 IV - "dtc", the device tree compiler
1057 ====================================
1060 dtc source code can be found at
1061 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1063 WARNING: This version is still in early development stage; the
1064 resulting device-tree "blobs" have not yet been validated with the
1065 kernel. The current generated bloc lacks a useful reserve map (it will
1066 be fixed to generate an empty one, it's up to the bootloader to fill
1067 it up) among others. The error handling needs work, bugs are lurking,
1070 dtc basically takes a device-tree in a given format and outputs a
1071 device-tree in another format. The currently supported formats are:
1076 - "dtb": "blob" format, that is a flattened device-tree block
1078 header all in a binary blob.
1079 - "dts": "source" format. This is a text file containing a
1080 "source" for a device-tree. The format is defined later in this
1082 - "fs" format. This is a representation equivalent to the
1083 output of /proc/device-tree, that is nodes are directories and
1084 properties are files
1089 - "dtb": "blob" format
1090 - "dts": "source" format
1091 - "asm": assembly language file. This is a file that can be
1092 sourced by gas to generate a device-tree "blob". That file can
1093 then simply be added to your Makefile. Additionally, the
1094 assembly file exports some symbols that can be used.
1097 The syntax of the dtc tool is
1099 dtc [-I <input-format>] [-O <output-format>]
1100 [-o output-filename] [-V output_version] input_filename
1103 The "output_version" defines what version of the "blob" format will be
1104 generated. Supported versions are 1,2,3 and 16. The default is
1105 currently version 3 but that may change in the future to version 16.
1107 Additionally, dtc performs various sanity checks on the tree, like the
1108 uniqueness of linux, phandle properties, validity of strings, etc...
1110 The format of the .dts "source" file is "C" like, supports C and C++
1116 The above is the "device-tree" definition. It's the only statement
1117 supported currently at the toplevel.
1120 property1 = "string_value"; /* define a property containing a 0
1124 property2 = <1234abcd>; /* define a property containing a
1125 * numerical 32-bit value (hexadecimal)
1128 property3 = <12345678 12345678 deadbeef>;
1129 /* define a property containing 3
1130 * numerical 32-bit values (cells) in
1133 property4 = [0a 0b 0c 0d de ea ad be ef];
1134 /* define a property whose content is
1135 * an arbitrary array of bytes
1138 childnode@addresss { /* define a child node named "childnode"
1139 * whose unit name is "childnode at
1143 childprop = "hello\n"; /* define a property "childprop" of
1144 * childnode (in this case, a string)
1149 Nodes can contain other nodes etc... thus defining the hierarchical
1150 structure of the tree.
1152 Strings support common escape sequences from C: "\n", "\t", "\r",
1153 "\(octal value)", "\x(hex value)".
1155 It is also suggested that you pipe your source file through cpp (gcc
1156 preprocessor) so you can use #include's, #define for constants, etc...
1158 Finally, various options are planned but not yet implemented, like
1159 automatic generation of phandles, labels (exported to the asm file so
1160 you can point to a property content and change it easily from whatever
1161 you link the device-tree with), label or path instead of numeric value
1162 in some cells to "point" to a node (replaced by a phandle at compile
1163 time), export of reserve map address to the asm file, ability to
1164 specify reserve map content at compile time, etc...
1166 We may provide a .h include file with common definitions of that
1167 proves useful for some properties (like building PCI properties or
1168 interrupt maps) though it may be better to add a notion of struct
1169 definitions to the compiler...
1172 V - Recommendations for a bootloader
1173 ====================================
1176 Here are some various ideas/recommendations that have been proposed
1177 while all this has been defined and implemented.
1179 - The bootloader may want to be able to use the device-tree itself
1180 and may want to manipulate it (to add/edit some properties,
1181 like physical memory size or kernel arguments). At this point, 2
1182 choices can be made. Either the bootloader works directly on the
1183 flattened format, or the bootloader has its own internal tree
1184 representation with pointers (similar to the kernel one) and
1185 re-flattens the tree when booting the kernel. The former is a bit
1186 more difficult to edit/modify, the later requires probably a bit
1187 more code to handle the tree structure. Note that the structure
1188 format has been designed so it's relatively easy to "insert"
1189 properties or nodes or delete them by just memmoving things
1190 around. It contains no internal offsets or pointers for this
1193 - An example of code for iterating nodes & retrieving properties
1194 directly from the flattened tree format can be found in the kernel
1195 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1196 its usage in early_init_devtree(), and the corresponding various
1197 early_init_dt_scan_*() callbacks. That code can be re-used in a
1198 GPL bootloader, and as the author of that code, I would be happy
1199 to discuss possible free licensing to any vendor who wishes to
1200 integrate all or part of this code into a non-GPL bootloader.
1204 VI - System-on-a-chip devices and nodes
1205 =======================================
1207 Many companies are now starting to develop system-on-a-chip
1208 processors, where the processor core (CPU) and many peripheral devices
1209 exist on a single piece of silicon. For these SOCs, an SOC node
1210 should be used that defines child nodes for the devices that make
1211 up the SOC. While platforms are not required to use this model in
1212 order to boot the kernel, it is highly encouraged that all SOC
1213 implementations define as complete a flat-device-tree as possible to
1214 describe the devices on the SOC. This will allow for the
1215 genericization of much of the kernel code.
1218 1) Defining child nodes of an SOC
1219 ---------------------------------
1221 Each device that is part of an SOC may have its own node entry inside
1222 the SOC node. For each device that is included in the SOC, the unit
1223 address property represents the address offset for this device's
1224 memory-mapped registers in the parent's address space. The parent's
1225 address space is defined by the "ranges" property in the top-level soc
1226 node. The "reg" property for each node that exists directly under the
1227 SOC node should contain the address mapping from the child address space
1228 to the parent SOC address space and the size of the device's
1229 memory-mapped register file.
1231 For many devices that may exist inside an SOC, there are predefined
1232 specifications for the format of the device tree node. All SOC child
1233 nodes should follow these specifications, except where noted in this
1236 See appendix A for an example partial SOC node definition for the
1240 2) Representing devices without a current OF specification
1241 ----------------------------------------------------------
1243 Currently, there are many devices on SOCs that do not have a standard
1244 representation pre-defined as part of the open firmware
1245 specifications, mainly because the boards that contain these SOCs are
1246 not currently booted using open firmware. This section contains
1247 descriptions for the SOC devices for which new nodes have been
1248 defined; this list will expand as more and more SOC-containing
1249 platforms are moved over to use the flattened-device-tree model.
1253 Required properties:
1255 - device_type : Should be "ethernet-phy"
1256 - interrupts : <a b> where a is the interrupt number and b is a
1257 field that represents an encoding of the sense and level
1258 information for the interrupt. This should be encoded based on
1259 the information in section 2) depending on the type of interrupt
1260 controller you have.
1261 - interrupt-parent : the phandle for the interrupt controller that
1262 services interrupts for this device.
1263 - reg : The ID number for the phy, usually a small integer
1264 - linux,phandle : phandle for this node; likely referenced by an
1265 ethernet controller node.
1271 linux,phandle = <2452000>
1272 interrupt-parent = <40000>;
1273 interrupts = <35 1>;
1275 device_type = "ethernet-phy";
1279 b) Interrupt controllers
1281 Some SOC devices contain interrupt controllers that are different
1282 from the standard Open PIC specification. The SOC device nodes for
1283 these types of controllers should be specified just like a standard
1284 OpenPIC controller. Sense and level information should be encoded
1285 as specified in section 2) of this chapter for each device that
1286 specifies an interrupt.
1291 linux,phandle = <40000>;
1292 interrupt-controller;
1293 #address-cells = <0>;
1294 reg = <40000 40000>;
1295 compatible = "chrp,open-pic";
1296 device_type = "open-pic";
1299 c) CFI or JEDEC memory-mapped NOR flash
1301 Flash chips (Memory Technology Devices) are often used for solid state
1302 file systems on embedded devices.
1304 - compatible : should contain the specific model of flash chip(s)
1305 used, if known, followed by either "cfi-flash" or "jedec-flash"
1306 - reg : Address range of the flash chip
1307 - bank-width : Width (in bytes) of the flash bank. Equal to the
1308 device width times the number of interleaved chips.
1309 - device-width : (optional) Width of a single flash chip. If
1310 omitted, assumed to be equal to 'bank-width'.
1311 - #address-cells, #size-cells : Must be present if the flash has
1312 sub-nodes representing partitions (see below). In this case
1313 both #address-cells and #size-cells must be equal to 1.
1315 For JEDEC compatible devices, the following additional properties
1318 - vendor-id : Contains the flash chip's vendor id (1 byte).
1319 - device-id : Contains the flash chip's device id (1 byte).
1321 In addition to the information on the flash bank itself, the
1322 device tree may optionally contain additional information
1323 describing partitions of the flash address space. This can be
1324 used on platforms which have strong conventions about which
1325 portions of the flash are used for what purposes, but which don't
1326 use an on-flash partition table such as RedBoot.
1328 Each partition is represented as a sub-node of the flash device.
1329 Each node's name represents the name of the corresponding
1330 partition of the flash device.
1333 - reg : The partition's offset and size within the flash bank.
1334 - label : (optional) The label / name for this flash partition.
1335 If omitted, the label is taken from the node name (excluding
1337 - read-only : (optional) This parameter, if present, is a hint to
1338 Linux that this flash partition should only be mounted
1339 read-only. This is usually used for flash partitions
1340 containing early-boot firmware images or data which should not
1346 compatible = "amd,am29lv128ml", "cfi-flash";
1347 reg = <ff000000 01000000>;
1350 #address-cells = <1>;
1358 reg = <f80000 80000>;
1363 d) 4xx/Axon EMAC ethernet nodes
1365 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
1366 the Axon bridge. To operate this needs to interact with a ths
1367 special McMAL DMA controller, and sometimes an RGMII or ZMII
1368 interface. In addition to the nodes and properties described
1369 below, the node for the OPB bus on which the EMAC sits must have a
1370 correct clock-frequency property.
1372 i) The EMAC node itself
1374 Required properties:
1375 - device_type : "network"
1377 - compatible : compatible list, contains 2 entries, first is
1378 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
1379 405gp, Axon) and second is either "ibm,emac" or
1380 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
1382 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
1383 - interrupt-parent : optional, if needed for interrupt mapping
1384 - reg : <registers mapping>
1385 - local-mac-address : 6 bytes, MAC address
1386 - mal-device : phandle of the associated McMAL node
1387 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
1389 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
1391 - cell-index : 1 cell, hardware index of the EMAC cell on a given
1392 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
1394 - max-frame-size : 1 cell, maximum frame size supported in bytes
1395 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
1398 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
1401 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
1403 For Axon, 0x00000010
1404 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
1406 For Axon, 0x00000100 (I think ...)
1407 - phy-mode : string, mode of operations of the PHY interface.
1408 Supported values are: "mii", "rmii", "smii", "rgmii",
1409 "tbi", "gmii", rtbi", "sgmii".
1410 For Axon on CAB, it is "rgmii"
1411 - mdio-device : 1 cell, required iff using shared MDIO registers
1412 (440EP). phandle of the EMAC to use to drive the
1413 MDIO lines for the PHY used by this EMAC.
1414 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
1415 the ZMII device node
1416 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
1417 channel or 0xffffffff if ZMII is only used for MDIO.
1418 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
1419 of the RGMII device node.
1420 For Axon: phandle of plb5/plb4/opb/rgmii
1421 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
1422 RGMII channel is used by this EMAC.
1423 Fox Axon: present, whatever value is appropriate for each
1424 EMAC, that is the content of the current (bogus) "phy-port"
1427 Optional properties:
1428 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
1429 a search is performed.
1430 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
1431 for, used if phy-address is absent. bit 0x00000001 is
1433 For Axon it can be absent, thouugh my current driver
1434 doesn't handle phy-address yet so for now, keep
1436 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
1437 operations (if absent the value is the same as
1438 rx-fifo-size). For Axon, either absent or 2048.
1439 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
1440 operations (if absent the value is the same as
1441 tx-fifo-size). For Axon, either absent or 2048.
1442 - tah-device : 1 cell, optional. If connected to a TAH engine for
1443 offload, phandle of the TAH device node.
1444 - tah-channel : 1 cell, optional. If appropriate, channel used on the
1449 EMAC0: ethernet@40000800 {
1450 device_type = "network";
1451 compatible = "ibm,emac-440gp", "ibm,emac";
1452 interrupt-parent = <&UIC1>;
1453 interrupts = <1c 4 1d 4>;
1454 reg = <40000800 70>;
1455 local-mac-address = [00 04 AC E3 1B 1E];
1456 mal-device = <&MAL0>;
1457 mal-tx-channel = <0 1>;
1458 mal-rx-channel = <0>;
1460 max-frame-size = <5dc>;
1461 rx-fifo-size = <1000>;
1462 tx-fifo-size = <800>;
1464 phy-map = <00000001>;
1465 zmii-device = <&ZMII0>;
1471 Required properties:
1472 - device_type : "dma-controller"
1473 - compatible : compatible list, containing 2 entries, first is
1474 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
1475 emac) and the second is either "ibm,mcmal" or
1477 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
1478 - interrupts : <interrupt mapping for the MAL interrupts sources:
1479 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
1480 For Axon: This is _different_ from the current
1481 firmware. We use the "delayed" interrupts for txeob
1482 and rxeob. Thus we end up with mapping those 5 MPIC
1483 interrupts, all level positive sensitive: 10, 11, 32,
1485 - dcr-reg : < DCR registers range >
1486 - dcr-parent : if needed for dcr-reg
1487 - num-tx-chans : 1 cell, number of Tx channels
1488 - num-rx-chans : 1 cell, number of Rx channels
1492 Required properties:
1493 - compatible : compatible list, containing 2 entries, first is
1494 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
1495 EMAC) and the second is "ibm,zmii".
1496 For Axon, there is no ZMII node.
1497 - reg : <registers mapping>
1501 Required properties:
1502 - compatible : compatible list, containing 2 entries, first is
1503 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
1504 EMAC) and the second is "ibm,rgmii".
1505 For Axon, "ibm,rgmii-axon","ibm,rgmii"
1506 - reg : <registers mapping>
1507 - revision : as provided by the RGMII new version register if
1509 For Axon: 0x0000012a
1513 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
1514 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
1515 of standard device types (network, serial, etc.) and miscellanious
1516 devices (gpio, LCD, spi, etc). Also, since these devices are
1517 implemented within the fpga fabric every instance of the device can be
1518 synthesised with different options that change the behaviour.
1520 Each IP-core has a set of parameters which the FPGA designer can use to
1521 control how the core is synthesized. Historically, the EDK tool would
1522 extract the device parameters relevant to device drivers and copy them
1523 into an 'xparameters.h' in the form of #define symbols. This tells the
1524 device drivers how the IP cores are configured, but it requres the kernel
1525 to be recompiled every time the FPGA bitstream is resynthesized.
1527 The new approach is to export the parameters into the device tree and
1528 generate a new device tree each time the FPGA bitstream changes. The
1529 parameters which used to be exported as #defines will now become
1530 properties of the device node. In general, device nodes for IP-cores
1531 will take the following form:
1533 (name): (generic-name)@(base-address) {
1534 compatible = "xlnx,(ip-core-name)-(HW_VER)"
1535 [, (list of compatible devices), ...];
1536 reg = <(baseaddr) (size)>;
1537 interrupt-parent = <&interrupt-controller-phandle>;
1538 interrupts = < ... >;
1539 xlnx,(parameter1) = "(string-value)";
1540 xlnx,(parameter2) = <(int-value)>;
1543 (generic-name): an open firmware-style name that describes the
1544 generic class of device. Preferably, this is one word, such
1545 as 'serial' or 'ethernet'.
1546 (ip-core-name): the name of the ip block (given after the BEGIN
1547 directive in system.mhs). Should be in lowercase
1548 and all underscores '_' converted to dashes '-'.
1549 (name): is derived from the "PARAMETER INSTANCE" value.
1550 (parameter#): C_* parameters from system.mhs. The C_ prefix is
1551 dropped from the parameter name, the name is converted
1552 to lowercase and all underscore '_' characters are
1553 converted to dashes '-'.
1554 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
1555 (HW_VER): from the HW_VER parameter.
1556 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
1558 Typically, the compatible list will include the exact IP core version
1559 followed by an older IP core version which implements the same
1560 interface or any other device with the same interface.
1562 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
1564 For example, the following block from system.mhs:
1567 PARAMETER INSTANCE = opb_uartlite_0
1568 PARAMETER HW_VER = 1.00.b
1569 PARAMETER C_BAUDRATE = 115200
1570 PARAMETER C_DATA_BITS = 8
1571 PARAMETER C_ODD_PARITY = 0
1572 PARAMETER C_USE_PARITY = 0
1573 PARAMETER C_CLK_FREQ = 50000000
1574 PARAMETER C_BASEADDR = 0xEC100000
1575 PARAMETER C_HIGHADDR = 0xEC10FFFF
1576 BUS_INTERFACE SOPB = opb_7
1577 PORT OPB_Clk = CLK_50MHz
1578 PORT Interrupt = opb_uartlite_0_Interrupt
1579 PORT RX = opb_uartlite_0_RX
1580 PORT TX = opb_uartlite_0_TX
1581 PORT OPB_Rst = sys_bus_reset_0
1584 becomes the following device tree node:
1586 opb_uartlite_0: serial@ec100000 {
1587 device_type = "serial";
1588 compatible = "xlnx,opb-uartlite-1.00.b";
1589 reg = <ec100000 10000>;
1590 interrupt-parent = <&opb_intc_0>;
1591 interrupts = <1 0>; // got this from the opb_intc parameters
1592 current-speed = <d#115200>; // standard serial device prop
1593 clock-frequency = <d#50000000>; // standard serial device prop
1594 xlnx,data-bits = <8>;
1595 xlnx,odd-parity = <0>;
1596 xlnx,use-parity = <0>;
1599 Some IP cores actually implement 2 or more logical devices. In
1600 this case, the device should still describe the whole IP core with
1601 a single node and add a child node for each logical device. The
1602 ranges property can be used to translate from parent IP-core to the
1603 registers of each device. In addition, the parent node should be
1604 compatible with the bus type 'xlnx,compound', and should contain
1605 #address-cells and #size-cells, as with any other bus. (Note: this
1606 makes the assumption that both logical devices have the same bus
1607 binding. If this is not true, then separate nodes should be used
1608 for each logical device). The 'cell-index' property can be used to
1609 enumerate logical devices within an IP core. For example, the
1610 following is the system.mhs entry for the dual ps2 controller found
1611 on the ml403 reference design.
1613 BEGIN opb_ps2_dual_ref
1614 PARAMETER INSTANCE = opb_ps2_dual_ref_0
1615 PARAMETER HW_VER = 1.00.a
1616 PARAMETER C_BASEADDR = 0xA9000000
1617 PARAMETER C_HIGHADDR = 0xA9001FFF
1618 BUS_INTERFACE SOPB = opb_v20_0
1619 PORT Sys_Intr1 = ps2_1_intr
1620 PORT Sys_Intr2 = ps2_2_intr
1621 PORT Clkin1 = ps2_clk_rx_1
1622 PORT Clkin2 = ps2_clk_rx_2
1623 PORT Clkpd1 = ps2_clk_tx_1
1624 PORT Clkpd2 = ps2_clk_tx_2
1625 PORT Rx1 = ps2_d_rx_1
1626 PORT Rx2 = ps2_d_rx_2
1627 PORT Txpd1 = ps2_d_tx_1
1628 PORT Txpd2 = ps2_d_tx_2
1631 It would result in the following device tree nodes:
1633 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
1634 #address-cells = <1>;
1636 compatible = "xlnx,compound";
1637 ranges = <0 a9000000 2000>;
1638 // If this device had extra parameters, then they would
1641 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1643 interrupt-parent = <&opb_intc_0>;
1648 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
1650 interrupt-parent = <&opb_intc_0>;
1656 Also, the system.mhs file defines bus attachments from the processor
1657 to the devices. The device tree structure should reflect the bus
1658 attachments. Again an example; this system.mhs fragment:
1660 BEGIN ppc405_virtex4
1661 PARAMETER INSTANCE = ppc405_0
1662 PARAMETER HW_VER = 1.01.a
1663 BUS_INTERFACE DPLB = plb_v34_0
1664 BUS_INTERFACE IPLB = plb_v34_0
1668 PARAMETER INSTANCE = opb_intc_0
1669 PARAMETER HW_VER = 1.00.c
1670 PARAMETER C_BASEADDR = 0xD1000FC0
1671 PARAMETER C_HIGHADDR = 0xD1000FDF
1672 BUS_INTERFACE SOPB = opb_v20_0
1676 PARAMETER INSTANCE = opb_uart16550_0
1677 PARAMETER HW_VER = 1.00.d
1678 PARAMETER C_BASEADDR = 0xa0000000
1679 PARAMETER C_HIGHADDR = 0xa0001FFF
1680 BUS_INTERFACE SOPB = opb_v20_0
1684 PARAMETER INSTANCE = plb_v34_0
1685 PARAMETER HW_VER = 1.02.a
1688 BEGIN plb_bram_if_cntlr
1689 PARAMETER INSTANCE = plb_bram_if_cntlr_0
1690 PARAMETER HW_VER = 1.00.b
1691 PARAMETER C_BASEADDR = 0xFFFF0000
1692 PARAMETER C_HIGHADDR = 0xFFFFFFFF
1693 BUS_INTERFACE SPLB = plb_v34_0
1696 BEGIN plb2opb_bridge
1697 PARAMETER INSTANCE = plb2opb_bridge_0
1698 PARAMETER HW_VER = 1.01.a
1699 PARAMETER C_RNG0_BASEADDR = 0x20000000
1700 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
1701 PARAMETER C_RNG1_BASEADDR = 0x60000000
1702 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
1703 PARAMETER C_RNG2_BASEADDR = 0x80000000
1704 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
1705 PARAMETER C_RNG3_BASEADDR = 0xC0000000
1706 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
1707 BUS_INTERFACE SPLB = plb_v34_0
1708 BUS_INTERFACE MOPB = opb_v20_0
1711 Gives this device tree (some properties removed for clarity):
1714 #address-cells = <1>;
1716 compatible = "xlnx,plb-v34-1.02.a";
1717 device_type = "ibm,plb";
1718 ranges; // 1:1 translation
1720 plb_bram_if_cntrl_0: bram@ffff0000 {
1721 reg = <ffff0000 10000>;
1725 #address-cells = <1>;
1727 ranges = <20000000 20000000 20000000
1728 60000000 60000000 20000000
1729 80000000 80000000 40000000
1730 c0000000 c0000000 20000000>;
1732 opb_uart16550_0: serial@a0000000 {
1733 reg = <a00000000 2000>;
1736 opb_intc_0: interrupt-controller@d1000fc0 {
1737 reg = <d1000fc0 20>;
1742 That covers the general approach to binding xilinx IP cores into the
1743 device tree. The following are bindings for specific devices:
1745 i) Xilinx ML300 Framebuffer
1747 Simple framebuffer device from the ML300 reference design (also on the
1748 ML403 reference design as well as others).
1750 Optional properties:
1751 - resolution = <xres yres> : pixel resolution of framebuffer. Some
1752 implementations use a different resolution.
1753 Default is <d#640 d#480>
1754 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
1755 Default is <d#1024 d#480>.
1756 - rotate-display (empty) : rotate display 180 degrees.
1758 ii) Xilinx SystemACE
1760 The Xilinx SystemACE device is used to program FPGAs from an FPGA
1761 bitstream stored on a CF card. It can also be used as a generic CF
1764 Optional properties:
1765 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
1767 iii) Xilinx EMAC and Xilinx TEMAC
1769 Xilinx Ethernet devices. In addition to general xilinx properties
1770 listed above, nodes for these devices should include a phy-handle
1771 property, and may include other common network device properties
1772 like local-mac-address.
1776 Xilinx uartlite devices are simple fixed speed serial ports.
1779 - current-speed : Baud rate of uartlite
1783 Xilinx hwicap devices provide access to the configuration logic
1784 of the FPGA through the Internal Configuration Access Port
1785 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
1786 readback of the configuration information, and some control over
1787 'warm boots' of the FPGA fabric.
1789 Required properties:
1790 - xlnx,family : The family of the FPGA, necessary since the
1791 capabilities of the underlying ICAP hardware
1792 differ between different families. May be
1793 'virtex2p', 'virtex4', or 'virtex5'.
1795 vi) Xilinx Uart 16550
1797 Xilinx UART 16550 devices are very similar to the NS16550 but with
1798 different register spacing and an offset from the base address.
1801 - clock-frequency : Frequency of the clock input
1802 - reg-offset : A value of 3 is required
1803 - reg-shift : A value of 2 is required
1805 f) USB EHCI controllers
1807 Required properties:
1808 - compatible : should be "usb-ehci".
1809 - reg : should contain at least address and length of the standard EHCI
1810 register set for the device. Optional platform-dependent registers
1811 (debug-port or other) can be also specified here, but only after
1812 definition of standard EHCI registers.
1813 - interrupts : one EHCI interrupt should be described here.
1814 If device registers are implemented in big endian mode, the device
1815 node should have "big-endian-regs" property.
1816 If controller implementation operates with big endian descriptors,
1817 "big-endian-desc" property should be specified.
1818 If both big endian registers and descriptors are used by the controller
1819 implementation, "big-endian" property can be specified instead of having
1820 both "big-endian-regs" and "big-endian-desc".
1822 Example (Sequoia 440EPx):
1824 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
1825 interrupt-parent = <&UIC0>;
1826 interrupts = <1a 4>;
1827 reg = <0 e0000300 90 0 e0000390 70>;
1831 r) Freescale Display Interface Unit
1833 The Freescale DIU is a LCD controller, with proper hardware, it can also
1836 Required properties:
1837 - compatible : should be "fsl-diu".
1838 - reg : should contain at least address and length of the DIU register
1840 - Interrupts : one DIU interrupt should be describe here.
1842 Example (MPC8610HPCD)
1844 compatible = "fsl,diu";
1845 reg = <0x2c000 100>;
1846 interrupts = <72 2>;
1847 interrupt-parent = <&mpic>;
1850 s) Freescale on board FPGA
1852 This is the memory-mapped registers for on board FPGA.
1854 Required properities:
1855 - compatible : should be "fsl,fpga-pixis".
1856 - reg : should contain the address and the lenght of the FPPGA register
1859 Example (MPC8610HPCD)
1860 board-control@e8000000 {
1861 compatible = "fsl,fpga-pixis";
1862 reg = <0xe8000000 32>;
1867 Currently defined compatibles:
1870 MDC and MDIO lines connected to GPIO controllers are listed in the
1871 gpios property as described in section VIII.1 in the following order:
1878 compatible = "virtual,mdio-gpio";
1879 #address-cells = <1>;
1881 gpios = <&qe_pio_a 11
1885 s) SPI (Serial Peripheral Interface) busses
1887 SPI busses can be described with a node for the SPI master device
1888 and a set of child nodes for each SPI slave on the bus. For this
1889 discussion, it is assumed that the system's SPI controller is in
1890 SPI master mode. This binding does not describe SPI controllers
1893 The SPI master node requires the following properties:
1894 - #address-cells - number of cells required to define a chip select
1895 address on the SPI bus.
1896 - #size-cells - should be zero.
1897 - compatible - name of SPI bus controller following generic names
1898 recommended practice.
1899 No other properties are required in the SPI bus node. It is assumed
1900 that a driver for an SPI bus device will understand that it is an SPI bus.
1901 However, the binding does not attempt to define the specific method for
1902 assigning chip select numbers. Since SPI chip select configuration is
1903 flexible and non-standardized, it is left out of this binding with the
1904 assumption that board specific platform code will be used to manage
1905 chip selects. Individual drivers can define additional properties to
1906 support describing the chip select layout.
1908 SPI slave nodes must be children of the SPI master node and can
1909 contain the following properties.
1910 - reg - (required) chip select address of device.
1911 - compatible - (required) name of SPI device following generic names
1912 recommended practice
1913 - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
1914 - spi-cpol - (optional) Empty property indicating device requires
1915 inverse clock polarity (CPOL) mode
1916 - spi-cpha - (optional) Empty property indicating device requires
1917 shifted clock phase (CPHA) mode
1919 SPI example for an MPC5200 SPI bus:
1921 #address-cells = <1>;
1923 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
1925 interrupts = <2 13 0 2 14 0>;
1926 interrupt-parent = <&mpc5200_pic>;
1929 compatible = "micrel,ks8995m";
1930 spi-max-frequency = <1000000>;
1935 compatible = "ti,tlv320aic26";
1936 spi-max-frequency = <100000>;
1941 VII - Marvell Discovery mv64[345]6x System Controller chips
1942 ===========================================================
1944 The Marvell mv64[345]60 series of system controller chips contain
1945 many of the peripherals needed to implement a complete computer
1946 system. In this section, we define device tree nodes to describe
1947 the system controller chip itself and each of the peripherals
1948 which it contains. Compatible string values for each node are
1949 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
1951 1) The /system-controller node
1953 This node is used to represent the system-controller and must be
1954 present when the system uses a system contller chip. The top-level
1955 system-controller node contains information that is global to all
1956 devices within the system controller chip. The node name begins
1957 with "system-controller" followed by the unit address, which is
1958 the base address of the memory-mapped register set for the system
1961 Required properties:
1963 - ranges : Describes the translation of system controller addresses
1964 for memory mapped registers.
1965 - clock-frequency: Contains the main clock frequency for the system
1967 - reg : This property defines the address and size of the
1968 memory-mapped registers contained within the system controller
1969 chip. The address specified in the "reg" property should match
1970 the unit address of the system-controller node.
1971 - #address-cells : Address representation for system controller
1972 devices. This field represents the number of cells needed to
1973 represent the address of the memory-mapped registers of devices
1974 within the system controller chip.
1975 - #size-cells : Size representation for for the memory-mapped
1976 registers within the system controller chip.
1977 - #interrupt-cells : Defines the width of cells used to represent
1980 Optional properties:
1982 - model : The specific model of the system controller chip. Such
1983 as, "mv64360", "mv64460", or "mv64560".
1984 - compatible : A string identifying the compatibility identifiers
1985 of the system controller chip.
1987 The system-controller node contains child nodes for each system
1988 controller device that the platform uses. Nodes should not be created
1989 for devices which exist on the system controller chip but are not used
1991 Example Marvell Discovery mv64360 system-controller node:
1993 system-controller@f1000000 { /* Marvell Discovery mv64360 */
1994 #address-cells = <1>;
1996 model = "mv64360"; /* Default */
1997 compatible = "marvell,mv64360";
1998 clock-frequency = <133333333>;
1999 reg = <0xf1000000 0x10000>;
2000 virtual-reg = <0xf1000000>;
2001 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
2002 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
2003 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
2004 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
2005 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
2007 [ child node definitions... ]
2010 2) Child nodes of /system-controller
2012 a) Marvell Discovery MDIO bus
2014 The MDIO is a bus to which the PHY devices are connected. For each
2015 device that exists on this bus, a child node should be created. See
2016 the definition of the PHY node below for an example of how to define
2019 Required properties:
2020 - #address-cells : Should be <1>
2021 - #size-cells : Should be <0>
2022 - device_type : Should be "mdio"
2023 - compatible : Should be "marvell,mv64360-mdio"
2028 #address-cells = <1>;
2030 device_type = "mdio";
2031 compatible = "marvell,mv64360-mdio";
2039 b) Marvell Discovery ethernet controller
2041 The Discover ethernet controller is described with two levels
2042 of nodes. The first level describes an ethernet silicon block
2043 and the second level describes up to 3 ethernet nodes within
2044 that block. The reason for the multiple levels is that the
2045 registers for the node are interleaved within a single set
2046 of registers. The "ethernet-block" level describes the
2047 shared register set, and the "ethernet" nodes describe ethernet
2048 port-specific properties.
2052 Required properties:
2053 - #address-cells : <1>
2055 - compatible : "marvell,mv64360-eth-block"
2056 - reg : Offset and length of the register set for this block
2058 Example Discovery Ethernet block node:
2059 ethernet-block@2000 {
2060 #address-cells = <1>;
2062 compatible = "marvell,mv64360-eth-block";
2063 reg = <0x2000 0x2000>;
2071 Required properties:
2072 - device_type : Should be "network".
2073 - compatible : Should be "marvell,mv64360-eth".
2074 - reg : Should be <0>, <1>, or <2>, according to which registers
2075 within the silicon block the device uses.
2076 - interrupts : <a> where a is the interrupt number for the port.
2077 - interrupt-parent : the phandle for the interrupt controller
2078 that services interrupts for this device.
2079 - phy : the phandle for the PHY connected to this ethernet
2081 - local-mac-address : 6 bytes, MAC address
2083 Example Discovery Ethernet port node:
2085 device_type = "network";
2086 compatible = "marvell,mv64360-eth";
2089 interrupt-parent = <&PIC>;
2091 local-mac-address = [ 00 00 00 00 00 00 ];
2096 c) Marvell Discovery PHY nodes
2098 Required properties:
2099 - device_type : Should be "ethernet-phy"
2100 - interrupts : <a> where a is the interrupt number for this phy.
2101 - interrupt-parent : the phandle for the interrupt controller that
2102 services interrupts for this device.
2103 - reg : The ID number for the phy, usually a small integer
2105 Example Discovery PHY node:
2107 device_type = "ethernet-phy";
2108 compatible = "broadcom,bcm5421";
2109 interrupts = <76>; /* GPP 12 */
2110 interrupt-parent = <&PIC>;
2115 d) Marvell Discovery SDMA nodes
2117 Represent DMA hardware associated with the MPSC (multiprotocol
2118 serial controllers).
2120 Required properties:
2121 - compatible : "marvell,mv64360-sdma"
2122 - reg : Offset and length of the register set for this device
2123 - interrupts : <a> where a is the interrupt number for the DMA
2125 - interrupt-parent : the phandle for the interrupt controller
2126 that services interrupts for this device.
2128 Example Discovery SDMA node:
2130 compatible = "marvell,mv64360-sdma";
2131 reg = <0x4000 0xc18>;
2132 virtual-reg = <0xf1004000>;
2134 interrupt-parent = <&PIC>;
2138 e) Marvell Discovery BRG nodes
2140 Represent baud rate generator hardware associated with the MPSC
2141 (multiprotocol serial controllers).
2143 Required properties:
2144 - compatible : "marvell,mv64360-brg"
2145 - reg : Offset and length of the register set for this device
2146 - clock-src : A value from 0 to 15 which selects the clock
2147 source for the baud rate generator. This value corresponds
2148 to the CLKS value in the BRGx configuration register. See
2149 the mv64x60 User's Manual.
2150 - clock-frequence : The frequency (in Hz) of the baud rate
2151 generator's input clock.
2152 - current-speed : The current speed setting (presumably by
2153 firmware) of the baud rate generator.
2155 Example Discovery BRG node:
2157 compatible = "marvell,mv64360-brg";
2160 clock-frequency = <133333333>;
2161 current-speed = <9600>;
2165 f) Marvell Discovery CUNIT nodes
2167 Represent the Serial Communications Unit device hardware.
2169 Required properties:
2170 - reg : Offset and length of the register set for this device
2172 Example Discovery CUNIT node:
2174 reg = <0xf200 0x200>;
2178 g) Marvell Discovery MPSCROUTING nodes
2180 Represent the Discovery's MPSC routing hardware
2182 Required properties:
2183 - reg : Offset and length of the register set for this device
2185 Example Discovery CUNIT node:
2191 h) Marvell Discovery MPSCINTR nodes
2193 Represent the Discovery's MPSC DMA interrupt hardware registers
2194 (SDMA cause and mask registers).
2196 Required properties:
2197 - reg : Offset and length of the register set for this device
2199 Example Discovery MPSCINTR node:
2201 reg = <0xb800 0x100>;
2205 i) Marvell Discovery MPSC nodes
2207 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
2210 Required properties:
2211 - device_type : "serial"
2212 - compatible : "marvell,mv64360-mpsc"
2213 - reg : Offset and length of the register set for this device
2214 - sdma : the phandle for the SDMA node used by this port
2215 - brg : the phandle for the BRG node used by this port
2216 - cunit : the phandle for the CUNIT node used by this port
2217 - mpscrouting : the phandle for the MPSCROUTING node used by this port
2218 - mpscintr : the phandle for the MPSCINTR node used by this port
2219 - cell-index : the hardware index of this cell in the MPSC core
2220 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
2222 - interrupts : <a> where a is the interrupt number for the MPSC.
2223 - interrupt-parent : the phandle for the interrupt controller
2224 that services interrupts for this device.
2226 Example Discovery MPSCINTR node:
2228 device_type = "serial";
2229 compatible = "marvell,mv64360-mpsc";
2230 reg = <0x8000 0x38>;
2231 virtual-reg = <0xf1008000>;
2235 mpscrouting = <&MPSCROUTING>;
2236 mpscintr = <&MPSCINTR>;
2240 interrupt-parent = <&PIC>;
2244 j) Marvell Discovery Watch Dog Timer nodes
2246 Represent the Discovery's watchdog timer hardware
2248 Required properties:
2249 - compatible : "marvell,mv64360-wdt"
2250 - reg : Offset and length of the register set for this device
2252 Example Discovery Watch Dog Timer node:
2254 compatible = "marvell,mv64360-wdt";
2259 k) Marvell Discovery I2C nodes
2261 Represent the Discovery's I2C hardware
2263 Required properties:
2264 - device_type : "i2c"
2265 - compatible : "marvell,mv64360-i2c"
2266 - reg : Offset and length of the register set for this device
2267 - interrupts : <a> where a is the interrupt number for the I2C.
2268 - interrupt-parent : the phandle for the interrupt controller
2269 that services interrupts for this device.
2271 Example Discovery I2C node:
2272 compatible = "marvell,mv64360-i2c";
2273 reg = <0xc000 0x20>;
2274 virtual-reg = <0xf100c000>;
2276 interrupt-parent = <&PIC>;
2280 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
2282 Represent the Discovery's PIC hardware
2284 Required properties:
2285 - #interrupt-cells : <1>
2286 - #address-cells : <0>
2287 - compatible : "marvell,mv64360-pic"
2288 - reg : Offset and length of the register set for this device
2289 - interrupt-controller
2291 Example Discovery PIC node:
2293 #interrupt-cells = <1>;
2294 #address-cells = <0>;
2295 compatible = "marvell,mv64360-pic";
2297 interrupt-controller;
2301 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
2303 Represent the Discovery's MPP hardware
2305 Required properties:
2306 - compatible : "marvell,mv64360-mpp"
2307 - reg : Offset and length of the register set for this device
2309 Example Discovery MPP node:
2311 compatible = "marvell,mv64360-mpp";
2312 reg = <0xf000 0x10>;
2316 n) Marvell Discovery GPP (General Purpose Pins) nodes
2318 Represent the Discovery's GPP hardware
2320 Required properties:
2321 - compatible : "marvell,mv64360-gpp"
2322 - reg : Offset and length of the register set for this device
2324 Example Discovery GPP node:
2326 compatible = "marvell,mv64360-gpp";
2327 reg = <0xf100 0x20>;
2331 o) Marvell Discovery PCI host bridge node
2333 Represents the Discovery's PCI host bridge device. The properties
2334 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
2335 1275-1994. A typical value for the compatible property is
2336 "marvell,mv64360-pci".
2338 Example Discovery PCI host bridge node
2340 #address-cells = <3>;
2342 #interrupt-cells = <1>;
2343 device_type = "pci";
2344 compatible = "marvell,mv64360-pci";
2346 ranges = <0x01000000 0x0 0x0
2347 0x88000000 0x0 0x01000000
2348 0x02000000 0x0 0x80000000
2349 0x80000000 0x0 0x08000000>;
2350 bus-range = <0 255>;
2351 clock-frequency = <66000000>;
2352 interrupt-parent = <&PIC>;
2353 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
2356 0x5000 0 0 1 &PIC 80
2357 0x5000 0 0 2 &PIC 81
2358 0x5000 0 0 3 &PIC 91
2359 0x5000 0 0 4 &PIC 93
2362 0x5800 0 0 1 &PIC 91
2363 0x5800 0 0 2 &PIC 93
2364 0x5800 0 0 3 &PIC 80
2365 0x5800 0 0 4 &PIC 81
2368 0x6000 0 0 1 &PIC 91
2369 0x6000 0 0 2 &PIC 93
2370 0x6000 0 0 3 &PIC 80
2371 0x6000 0 0 4 &PIC 81
2374 0x6800 0 0 1 &PIC 93
2375 0x6800 0 0 2 &PIC 80
2376 0x6800 0 0 3 &PIC 81
2377 0x6800 0 0 4 &PIC 91
2382 p) Marvell Discovery CPU Error nodes
2384 Represent the Discovery's CPU error handler device.
2386 Required properties:
2387 - compatible : "marvell,mv64360-cpu-error"
2388 - reg : Offset and length of the register set for this device
2389 - interrupts : the interrupt number for this device
2390 - interrupt-parent : the phandle for the interrupt controller
2391 that services interrupts for this device.
2393 Example Discovery CPU Error node:
2395 compatible = "marvell,mv64360-cpu-error";
2396 reg = <0x70 0x10 0x128 0x28>;
2398 interrupt-parent = <&PIC>;
2402 q) Marvell Discovery SRAM Controller nodes
2404 Represent the Discovery's SRAM controller device.
2406 Required properties:
2407 - compatible : "marvell,mv64360-sram-ctrl"
2408 - reg : Offset and length of the register set for this device
2409 - interrupts : the interrupt number for this device
2410 - interrupt-parent : the phandle for the interrupt controller
2411 that services interrupts for this device.
2413 Example Discovery SRAM Controller node:
2415 compatible = "marvell,mv64360-sram-ctrl";
2418 interrupt-parent = <&PIC>;
2422 r) Marvell Discovery PCI Error Handler nodes
2424 Represent the Discovery's PCI error handler device.
2426 Required properties:
2427 - compatible : "marvell,mv64360-pci-error"
2428 - reg : Offset and length of the register set for this device
2429 - interrupts : the interrupt number for this device
2430 - interrupt-parent : the phandle for the interrupt controller
2431 that services interrupts for this device.
2433 Example Discovery PCI Error Handler node:
2435 compatible = "marvell,mv64360-pci-error";
2436 reg = <0x1d40 0x40 0xc28 0x4>;
2438 interrupt-parent = <&PIC>;
2442 s) Marvell Discovery Memory Controller nodes
2444 Represent the Discovery's memory controller device.
2446 Required properties:
2447 - compatible : "marvell,mv64360-mem-ctrl"
2448 - reg : Offset and length of the register set for this device
2449 - interrupts : the interrupt number for this device
2450 - interrupt-parent : the phandle for the interrupt controller
2451 that services interrupts for this device.
2453 Example Discovery Memory Controller node:
2455 compatible = "marvell,mv64360-mem-ctrl";
2456 reg = <0x1400 0x60>;
2458 interrupt-parent = <&PIC>;
2462 VIII - Specifying interrupt information for devices
2463 ===================================================
2465 The device tree represents the busses and devices of a hardware
2466 system in a form similar to the physical bus topology of the
2469 In addition, a logical 'interrupt tree' exists which represents the
2470 hierarchy and routing of interrupts in the hardware.
2472 The interrupt tree model is fully described in the
2473 document "Open Firmware Recommended Practice: Interrupt
2474 Mapping Version 0.9". The document is available at:
2475 <http://playground.sun.com/1275/practice>.
2477 1) interrupts property
2478 ----------------------
2480 Devices that generate interrupts to a single interrupt controller
2481 should use the conventional OF representation described in the
2482 OF interrupt mapping documentation.
2484 Each device which generates interrupts must have an 'interrupt'
2485 property. The interrupt property value is an arbitrary number of
2486 of 'interrupt specifier' values which describe the interrupt or
2487 interrupts for the device.
2489 The encoding of an interrupt specifier is determined by the
2490 interrupt domain in which the device is located in the
2491 interrupt tree. The root of an interrupt domain specifies in
2492 its #interrupt-cells property the number of 32-bit cells
2493 required to encode an interrupt specifier. See the OF interrupt
2494 mapping documentation for a detailed description of domains.
2496 For example, the binding for the OpenPIC interrupt controller
2497 specifies an #interrupt-cells value of 2 to encode the interrupt
2498 number and level/sense information. All interrupt children in an
2499 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
2502 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
2503 which interrupt pin (INTA,INTB,INTC,INTD) is used.
2505 2) interrupt-parent property
2506 ----------------------------
2508 The interrupt-parent property is specified to define an explicit
2509 link between a device node and its interrupt parent in
2510 the interrupt tree. The value of interrupt-parent is the
2511 phandle of the parent node.
2513 If the interrupt-parent property is not defined for a node, it's
2514 interrupt parent is assumed to be an ancestor in the node's
2515 _device tree_ hierarchy.
2517 3) OpenPIC Interrupt Controllers
2518 --------------------------------
2520 OpenPIC interrupt controllers require 2 cells to encode
2521 interrupt information. The first cell defines the interrupt
2522 number. The second cell defines the sense and level
2525 Sense and level information should be encoded as follows:
2527 0 = low to high edge sensitive type enabled
2528 1 = active low level sensitive type enabled
2529 2 = active high level sensitive type enabled
2530 3 = high to low edge sensitive type enabled
2532 4) ISA Interrupt Controllers
2533 ----------------------------
2535 ISA PIC interrupt controllers require 2 cells to encode
2536 interrupt information. The first cell defines the interrupt
2537 number. The second cell defines the sense and level
2540 ISA PIC interrupt controllers should adhere to the ISA PIC
2541 encodings listed below:
2543 0 = active low level sensitive type enabled
2544 1 = active high level sensitive type enabled
2545 2 = high to low edge sensitive type enabled
2546 3 = low to high edge sensitive type enabled
2548 VIII - Specifying GPIO information for devices
2549 ==============================================
2554 Nodes that makes use of GPIOs should define them using `gpios' property,
2555 format of which is: <&gpio-controller1-phandle gpio1-specifier
2556 &gpio-controller2-phandle gpio2-specifier
2557 0 /* holes are permitted, means no GPIO 3 */
2558 &gpio-controller4-phandle gpio4-specifier
2561 Note that gpio-specifier length is controller dependent.
2563 gpio-specifier may encode: bank, pin position inside the bank,
2564 whether pin is open-drain and whether pin is logically inverted.
2566 Example of the node using GPIOs:
2569 gpios = <&qe_pio_e 18 0>;
2572 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
2573 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2575 2) gpio-controller nodes
2576 ------------------------
2578 Every GPIO controller node must have #gpio-cells property defined,
2579 this information will be used to translate gpio-specifiers.
2581 Example of two SOC GPIO banks defined as gpio-controller nodes:
2583 qe_pio_a: gpio-controller@1400 {
2585 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
2586 reg = <0x1400 0x18>;
2590 qe_pio_e: gpio-controller@1460 {
2592 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
2593 reg = <0x1460 0x18>;
2597 Appendix A - Sample SOC node for MPC8540
2598 ========================================
2600 Note that the #address-cells and #size-cells for the SoC node
2601 in this example have been explicitly listed; these are likely
2602 not necessary as they are usually the same as the root node.
2605 #address-cells = <1>;
2607 #interrupt-cells = <2>;
2608 device_type = "soc";
2609 ranges = <00000000 e0000000 00100000>
2610 reg = <e0000000 00003000>;
2611 bus-frequency = <0>;
2615 device_type = "mdio";
2616 compatible = "gianfar";
2619 linux,phandle = <2452000>
2620 interrupt-parent = <40000>;
2621 interrupts = <35 1>;
2623 device_type = "ethernet-phy";
2627 linux,phandle = <2452001>
2628 interrupt-parent = <40000>;
2629 interrupts = <35 1>;
2631 device_type = "ethernet-phy";
2635 linux,phandle = <2452002>
2636 interrupt-parent = <40000>;
2637 interrupts = <35 1>;
2639 device_type = "ethernet-phy";
2646 device_type = "network";
2648 compatible = "gianfar";
2650 mac-address = [ 00 E0 0C 00 73 00 ];
2651 interrupts = <d 3 e 3 12 3>;
2652 interrupt-parent = <40000>;
2653 phy-handle = <2452000>;
2657 #address-cells = <1>;
2659 device_type = "network";
2661 compatible = "gianfar";
2663 mac-address = [ 00 E0 0C 00 73 01 ];
2664 interrupts = <13 3 14 3 18 3>;
2665 interrupt-parent = <40000>;
2666 phy-handle = <2452001>;
2670 #address-cells = <1>;
2672 device_type = "network";
2674 compatible = "gianfar";
2676 mac-address = [ 00 E0 0C 00 73 02 ];
2677 interrupts = <19 3>;
2678 interrupt-parent = <40000>;
2679 phy-handle = <2452002>;
2683 device_type = "serial";
2684 compatible = "ns16550";
2686 clock-frequency = <0>;
2687 interrupts = <1a 3>;
2688 interrupt-parent = <40000>;
2692 linux,phandle = <40000>;
2693 interrupt-controller;
2694 #address-cells = <0>;
2695 reg = <40000 40000>;
2696 compatible = "chrp,open-pic";
2697 device_type = "open-pic";
2701 interrupt-parent = <40000>;
2702 interrupts = <1b 3>;
2704 device_type = "i2c";
2705 compatible = "fsl-i2c";