3 This document describes the Linux kernel Makefiles.
10 --- 3.1 Goal definitions
11 --- 3.2 Built-in object goals - obj-y
12 --- 3.3 Loadable module goals - obj-m
13 --- 3.4 Objects which export symbols
14 --- 3.5 Library file goals - lib-y
15 --- 3.6 Descending down in directories
16 --- 3.7 Compilation flags
17 --- 3.8 Command line dependency
18 --- 3.9 Dependency tracking
19 --- 3.10 Special Rules
20 --- 3.11 $(CC) support functions
22 === 4 Host Program support
23 --- 4.1 Simple Host Program
24 --- 4.2 Composite Host Programs
25 --- 4.3 Defining shared libraries
26 --- 4.4 Using C++ for host programs
27 --- 4.5 Controlling compiler options for host programs
28 --- 4.6 When host programs are actually built
29 --- 4.7 Using hostprogs-$(CONFIG_FOO)
31 === 5 Kbuild clean infrastructure
33 === 6 Architecture Makefiles
34 --- 6.1 Set variables to tweak the build to the architecture
35 --- 6.2 Add prerequisites to archprepare:
36 --- 6.3 List directories to visit when descending
37 --- 6.4 Architecture specific boot images
38 --- 6.5 Building non-kbuild targets
39 --- 6.6 Commands useful for building a boot image
40 --- 6.7 Custom kbuild commands
41 --- 6.8 Preprocessing linker scripts
43 === 7 Kbuild Variables
44 === 8 Makefile language
50 The Makefiles have five parts:
52 Makefile the top Makefile.
53 .config the kernel configuration file.
54 arch/$(ARCH)/Makefile the arch Makefile.
55 scripts/Makefile.* common rules etc. for all kbuild Makefiles.
56 kbuild Makefiles there are about 500 of these.
58 The top Makefile reads the .config file, which comes from the kernel
59 configuration process.
61 The top Makefile is responsible for building two major products: vmlinux
62 (the resident kernel image) and modules (any module files).
63 It builds these goals by recursively descending into the subdirectories of
64 the kernel source tree.
65 The list of subdirectories which are visited depends upon the kernel
66 configuration. The top Makefile textually includes an arch Makefile
67 with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
68 architecture-specific information to the top Makefile.
70 Each subdirectory has a kbuild Makefile which carries out the commands
71 passed down from above. The kbuild Makefile uses information from the
72 .config file to construct various file lists used by kbuild to build
73 any built-in or modular targets.
75 scripts/Makefile.* contains all the definitions/rules etc. that
76 are used to build the kernel based on the kbuild makefiles.
81 People have four different relationships with the kernel Makefiles.
83 *Users* are people who build kernels. These people type commands such as
84 "make menuconfig" or "make". They usually do not read or edit
85 any kernel Makefiles (or any other source files).
87 *Normal developers* are people who work on features such as device
88 drivers, file systems, and network protocols. These people need to
89 maintain the kbuild Makefiles for the subsystem they are
90 working on. In order to do this effectively, they need some overall
91 knowledge about the kernel Makefiles, plus detailed knowledge about the
92 public interface for kbuild.
94 *Arch developers* are people who work on an entire architecture, such
95 as sparc or ia64. Arch developers need to know about the arch Makefile
96 as well as kbuild Makefiles.
98 *Kbuild developers* are people who work on the kernel build system itself.
99 These people need to know about all aspects of the kernel Makefiles.
101 This document is aimed towards normal developers and arch developers.
104 === 3 The kbuild files
106 Most Makefiles within the kernel are kbuild Makefiles that use the
107 kbuild infrastructure. This chapter introduces the syntax used in the
109 The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
110 be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
113 Section 3.1 "Goal definitions" is a quick intro, further chapters provide
114 more details, with real examples.
116 --- 3.1 Goal definitions
118 Goal definitions are the main part (heart) of the kbuild Makefile.
119 These lines define the files to be built, any special compilation
120 options, and any subdirectories to be entered recursively.
122 The most simple kbuild makefile contains one line:
127 This tell kbuild that there is one object in that directory, named
128 foo.o. foo.o will be built from foo.c or foo.S.
130 If foo.o shall be built as a module, the variable obj-m is used.
131 Therefore the following pattern is often used:
134 obj-$(CONFIG_FOO) += foo.o
136 $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
137 If CONFIG_FOO is neither y nor m, then the file will not be compiled
140 --- 3.2 Built-in object goals - obj-y
142 The kbuild Makefile specifies object files for vmlinux
143 in the $(obj-y) lists. These lists depend on the kernel
146 Kbuild compiles all the $(obj-y) files. It then calls
147 "$(LD) -r" to merge these files into one built-in.o file.
148 built-in.o is later linked into vmlinux by the parent Makefile.
150 The order of files in $(obj-y) is significant. Duplicates in
151 the lists are allowed: the first instance will be linked into
152 built-in.o and succeeding instances will be ignored.
154 Link order is significant, because certain functions
155 (module_init() / __initcall) will be called during boot in the
156 order they appear. So keep in mind that changing the link
157 order may e.g. change the order in which your SCSI
158 controllers are detected, and thus your disks are renumbered.
161 #drivers/isdn/i4l/Makefile
162 # Makefile for the kernel ISDN subsystem and device drivers.
163 # Each configuration option enables a list of files.
164 obj-$(CONFIG_ISDN) += isdn.o
165 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
167 --- 3.3 Loadable module goals - obj-m
169 $(obj-m) specify object files which are built as loadable
172 A module may be built from one source file or several source
173 files. In the case of one source file, the kbuild makefile
174 simply adds the file to $(obj-m).
177 #drivers/isdn/i4l/Makefile
178 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
180 Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
182 If a kernel module is built from several source files, you specify
183 that you want to build a module in the same way as above.
185 Kbuild needs to know which the parts that you want to build your
186 module from, so you have to tell it by setting an
187 $(<module_name>-objs) variable.
190 #drivers/isdn/i4l/Makefile
191 obj-$(CONFIG_ISDN) += isdn.o
192 isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
194 In this example, the module name will be isdn.o. Kbuild will
195 compile the objects listed in $(isdn-objs) and then run
196 "$(LD) -r" on the list of these files to generate isdn.o.
198 Kbuild recognises objects used for composite objects by the suffix
199 -objs, and the suffix -y. This allows the Makefiles to use
200 the value of a CONFIG_ symbol to determine if an object is part
201 of a composite object.
205 obj-$(CONFIG_EXT2_FS) += ext2.o
206 ext2-y := balloc.o bitmap.o
207 ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
209 In this example, xattr.o is only part of the composite object
210 ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
212 Note: Of course, when you are building objects into the kernel,
213 the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
214 kbuild will build an ext2.o file for you out of the individual
215 parts and then link this into built-in.o, as you would expect.
217 --- 3.4 Objects which export symbols
219 No special notation is required in the makefiles for
220 modules exporting symbols.
222 --- 3.5 Library file goals - lib-y
224 Objects listed with obj-* are used for modules, or
225 combined in a built-in.o for that specific directory.
226 There is also the possibility to list objects that will
227 be included in a library, lib.a.
228 All objects listed with lib-y are combined in a single
229 library for that directory.
230 Objects that are listed in obj-y and additionaly listed in
231 lib-y will not be included in the library, since they will anyway
233 For consistency, objects listed in lib-m will be included in lib.a.
235 Note that the same kbuild makefile may list files to be built-in
236 and to be part of a library. Therefore the same directory
237 may contain both a built-in.o and a lib.a file.
240 #arch/i386/lib/Makefile
241 lib-y := checksum.o delay.o
243 This will create a library lib.a based on checksum.o and delay.o.
244 For kbuild to actually recognize that there is a lib.a being built,
245 the directory shall be listed in libs-y.
246 See also "6.3 List directories to visit when descending".
248 Use of lib-y is normally restricted to lib/ and arch/*/lib.
250 --- 3.6 Descending down in directories
252 A Makefile is only responsible for building objects in its own
253 directory. Files in subdirectories should be taken care of by
254 Makefiles in these subdirs. The build system will automatically
255 invoke make recursively in subdirectories, provided you let it know of
258 To do so, obj-y and obj-m are used.
259 ext2 lives in a separate directory, and the Makefile present in fs/
260 tells kbuild to descend down using the following assignment.
264 obj-$(CONFIG_EXT2_FS) += ext2/
266 If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
267 the corresponding obj- variable will be set, and kbuild will descend
268 down in the ext2 directory.
269 Kbuild only uses this information to decide that it needs to visit
270 the directory, it is the Makefile in the subdirectory that
271 specifies what is modules and what is built-in.
273 It is good practice to use a CONFIG_ variable when assigning directory
274 names. This allows kbuild to totally skip the directory if the
275 corresponding CONFIG_ option is neither 'y' nor 'm'.
277 --- 3.7 Compilation flags
279 EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS
281 All the EXTRA_ variables apply only to the kbuild makefile
282 where they are assigned. The EXTRA_ variables apply to all
283 commands executed in the kbuild makefile.
285 $(EXTRA_CFLAGS) specifies options for compiling C files with
289 # drivers/sound/emu10k1/Makefile
290 EXTRA_CFLAGS += -I$(obj)
292 EXTRA_CFLAGS += -DEMU10K1_DEBUG
296 This variable is necessary because the top Makefile owns the
297 variable $(CFLAGS) and uses it for compilation flags for the
300 $(EXTRA_AFLAGS) is a similar string for per-directory options
301 when compiling assembly language source.
304 #arch/x86_64/kernel/Makefile
305 EXTRA_AFLAGS := -traditional
308 $(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
309 per-directory options to $(LD) and $(AR).
312 #arch/m68k/fpsp040/Makefile
317 CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
320 $(CFLAGS_$@) specifies per-file options for $(CC). The $@
321 part has a literal value which specifies the file that it is for.
324 # drivers/scsi/Makefile
325 CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
326 CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
328 CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
330 These three lines specify compilation flags for aha152x.o,
331 gdth.o, and seagate.o
333 $(AFLAGS_$@) is a similar feature for source files in assembly
337 # arch/arm/kernel/Makefile
338 AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
339 AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
341 --- 3.9 Dependency tracking
343 Kbuild tracks dependencies on the following:
344 1) All prerequisite files (both *.c and *.h)
345 2) CONFIG_ options used in all prerequisite files
346 3) Command-line used to compile target
348 Thus, if you change an option to $(CC) all affected files will
351 --- 3.10 Special Rules
353 Special rules are used when the kbuild infrastructure does
354 not provide the required support. A typical example is
355 header files generated during the build process.
356 Another example are the architecture specific Makefiles which
357 need special rules to prepare boot images etc.
359 Special rules are written as normal Make rules.
360 Kbuild is not executing in the directory where the Makefile is
361 located, so all special rules shall provide a relative
362 path to prerequisite files and target files.
364 Two variables are used when defining special rules:
367 $(src) is a relative path which points to the directory
368 where the Makefile is located. Always use $(src) when
369 referring to files located in the src tree.
372 $(obj) is a relative path which points to the directory
373 where the target is saved. Always use $(obj) when
374 referring to generated files.
377 #drivers/scsi/Makefile
378 $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
379 $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
381 This is a special rule, following the normal syntax
383 The target file depends on two prerequisite files. References
384 to the target file are prefixed with $(obj), references
385 to prerequisites are referenced with $(src) (because they are not
388 --- 3.11 $(CC) support functions
390 The kernel may be built with several different versions of
391 $(CC), each supporting a unique set of features and options.
392 kbuild provide basic support to check for valid options for $(CC).
393 $(CC) is useally the gcc compiler, but other alternatives are
397 as-option is used to check if $(CC) -- when used to compile
398 assembler (*.S) files -- supports the given option. An optional
399 second option may be specified if the first option is not supported.
403 cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
405 In the above example, cflags-y will be assigned the option
406 -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
407 The second argument is optional, and if supplied will be used
408 if first argument is not supported.
411 ld-option is used to check if $(CC) when used to link object files
412 supports the given option. An optional second option may be
413 specified if first option are not supported.
416 #arch/i386/kernel/Makefile
417 vsyscall-flags += $(call ld-option, -Wl$(comma)--hash-style=sysv)
419 In the above example vsyscall-flags will be assigned the option
420 -Wl$(comma)--hash-style=sysv if it is supported by $(CC).
421 The second argument is optional, and if supplied will be used
422 if first argument is not supported.
425 cc-option is used to check if $(CC) supports a given option, and not
426 supported to use an optional second option.
430 cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
432 In the above example cflags-y will be assigned the option
433 -march=pentium-mmx if supported by $(CC), otherwise -march=i586.
434 The second argument to cc-option is optional, and if omitted,
435 cflags-y will be assigned no value if first option is not supported.
438 cc-option-yn is used to check if gcc supports a given option
439 and return 'y' if supported, otherwise 'n'.
443 biarch := $(call cc-option-yn, -m32)
444 aflags-$(biarch) += -a32
445 cflags-$(biarch) += -m32
447 In the above example, $(biarch) is set to y if $(CC) supports the -m32
448 option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
449 and $(cflags-y) will be assigned the values -a32 and -m32,
453 gcc versions >= 3.0 changed the type of options used to specify
454 alignment of functions, loops etc. $(cc-option-align), when used
455 as prefix to the align options, will select the right prefix:
457 cc-option-align = -malign
459 cc-option-align = -falign
462 CFLAGS += $(cc-option-align)-functions=4
464 In the above example, the option -falign-functions=4 is used for
465 gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
468 cc-version returns a numerical version of the $(CC) compiler version.
469 The format is <major><minor> where both are two digits. So for example
470 gcc 3.41 would return 0341.
471 cc-version is useful when a specific $(CC) version is faulty in one
472 area, for example -mregparm=3 was broken in some gcc versions
473 even though the option was accepted by gcc.
477 cflags-y += $(shell \
478 if [ $(call cc-version) -ge 0300 ] ; then \
479 echo "-mregparm=3"; fi ;)
481 In the above example, -mregparm=3 is only used for gcc version greater
482 than or equal to gcc 3.0.
485 cc-ifversion tests the version of $(CC) and equals last argument if
486 version expression is true.
489 #fs/reiserfs/Makefile
490 EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)
492 In this example, EXTRA_CFLAGS will be assigned the value -O1 if the
493 $(CC) version is less than 4.2.
494 cc-ifversion takes all the shell operators:
495 -eq, -ne, -lt, -le, -gt, and -ge
496 The third parameter may be a text as in this example, but it may also
497 be an expanded variable or a macro.
500 === 4 Host Program support
502 Kbuild supports building executables on the host for use during the
504 Two steps are required in order to use a host executable.
506 The first step is to tell kbuild that a host program exists. This is
507 done utilising the variable hostprogs-y.
509 The second step is to add an explicit dependency to the executable.
510 This can be done in two ways. Either add the dependency in a rule,
511 or utilise the variable $(always).
512 Both possibilities are described in the following.
514 --- 4.1 Simple Host Program
516 In some cases there is a need to compile and run a program on the
517 computer where the build is running.
518 The following line tells kbuild that the program bin2hex shall be
519 built on the build host.
522 hostprogs-y := bin2hex
524 Kbuild assumes in the above example that bin2hex is made from a single
525 c-source file named bin2hex.c located in the same directory as
528 --- 4.2 Composite Host Programs
530 Host programs can be made up based on composite objects.
531 The syntax used to define composite objects for host programs is
532 similar to the syntax used for kernel objects.
533 $(<executeable>-objs) lists all objects used to link the final
537 #scripts/lxdialog/Makefile
538 hostprogs-y := lxdialog
539 lxdialog-objs := checklist.o lxdialog.o
541 Objects with extension .o are compiled from the corresponding .c
542 files. In the above example, checklist.c is compiled to checklist.o
543 and lxdialog.c is compiled to lxdialog.o.
544 Finally, the two .o files are linked to the executable, lxdialog.
545 Note: The syntax <executable>-y is not permitted for host-programs.
547 --- 4.3 Defining shared libraries
549 Objects with extension .so are considered shared libraries, and
550 will be compiled as position independent objects.
551 Kbuild provides support for shared libraries, but the usage
553 In the following example the libkconfig.so shared library is used
554 to link the executable conf.
557 #scripts/kconfig/Makefile
559 conf-objs := conf.o libkconfig.so
560 libkconfig-objs := expr.o type.o
562 Shared libraries always require a corresponding -objs line, and
563 in the example above the shared library libkconfig is composed by
564 the two objects expr.o and type.o.
565 expr.o and type.o will be built as position independent code and
566 linked as a shared library libkconfig.so. C++ is not supported for
569 --- 4.4 Using C++ for host programs
571 kbuild offers support for host programs written in C++. This was
572 introduced solely to support kconfig, and is not recommended
576 #scripts/kconfig/Makefile
578 qconf-cxxobjs := qconf.o
580 In the example above the executable is composed of the C++ file
581 qconf.cc - identified by $(qconf-cxxobjs).
583 If qconf is composed by a mixture of .c and .cc files, then an
584 additional line can be used to identify this.
587 #scripts/kconfig/Makefile
589 qconf-cxxobjs := qconf.o
590 qconf-objs := check.o
592 --- 4.5 Controlling compiler options for host programs
594 When compiling host programs, it is possible to set specific flags.
595 The programs will always be compiled utilising $(HOSTCC) passed
596 the options specified in $(HOSTCFLAGS).
597 To set flags that will take effect for all host programs created
598 in that Makefile, use the variable HOST_EXTRACFLAGS.
601 #scripts/lxdialog/Makefile
602 HOST_EXTRACFLAGS += -I/usr/include/ncurses
604 To set specific flags for a single file the following construction
608 #arch/ppc64/boot/Makefile
609 HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
611 It is also possible to specify additional options to the linker.
614 #scripts/kconfig/Makefile
615 HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
617 When linking qconf, it will be passed the extra option
620 --- 4.6 When host programs are actually built
622 Kbuild will only build host-programs when they are referenced
624 This is possible in two ways:
626 (1) List the prerequisite explicitly in a special rule.
629 #drivers/pci/Makefile
630 hostprogs-y := gen-devlist
631 $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
632 ( cd $(obj); ./gen-devlist ) < $<
634 The target $(obj)/devlist.h will not be built before
635 $(obj)/gen-devlist is updated. Note that references to
636 the host programs in special rules must be prefixed with $(obj).
639 When there is no suitable special rule, and the host program
640 shall be built when a makefile is entered, the $(always)
641 variable shall be used.
644 #scripts/lxdialog/Makefile
645 hostprogs-y := lxdialog
646 always := $(hostprogs-y)
648 This will tell kbuild to build lxdialog even if not referenced in
651 --- 4.7 Using hostprogs-$(CONFIG_FOO)
653 A typcal pattern in a Kbuild file looks like this:
657 hostprogs-$(CONFIG_KALLSYMS) += kallsyms
659 Kbuild knows about both 'y' for built-in and 'm' for module.
660 So if a config symbol evaluate to 'm', kbuild will still build
661 the binary. In other words, Kbuild handles hostprogs-m exactly
662 like hostprogs-y. But only hostprogs-y is recommended to be used
663 when no CONFIG symbols are involved.
665 === 5 Kbuild clean infrastructure
667 "make clean" deletes most generated files in the obj tree where the kernel
668 is compiled. This includes generated files such as host programs.
669 Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
670 $(extra-y) and $(targets). They are all deleted during "make clean".
671 Files matching the patterns "*.[oas]", "*.ko", plus some additional files
672 generated by kbuild are deleted all over the kernel src tree when
673 "make clean" is executed.
675 Additional files can be specified in kbuild makefiles by use of $(clean-files).
678 #drivers/pci/Makefile
679 clean-files := devlist.h classlist.h
681 When executing "make clean", the two files "devlist.h classlist.h" will
682 be deleted. Kbuild will assume files to be in same relative directory as the
683 Makefile except if an absolute path is specified (path starting with '/').
685 To delete a directory hirachy use:
687 #scripts/package/Makefile
688 clean-dirs := $(objtree)/debian/
690 This will delete the directory debian, including all subdirectories.
691 Kbuild will assume the directories to be in the same relative path as the
692 Makefile if no absolute path is specified (path does not start with '/').
694 Usually kbuild descends down in subdirectories due to "obj-* := dir/",
695 but in the architecture makefiles where the kbuild infrastructure
696 is not sufficient this sometimes needs to be explicit.
699 #arch/i386/boot/Makefile
700 subdir- := compressed/
702 The above assignment instructs kbuild to descend down in the
703 directory compressed/ when "make clean" is executed.
705 To support the clean infrastructure in the Makefiles that builds the
706 final bootimage there is an optional target named archclean:
711 $(Q)$(MAKE) $(clean)=arch/i386/boot
713 When "make clean" is executed, make will descend down in arch/i386/boot,
714 and clean as usual. The Makefile located in arch/i386/boot/ may use
715 the subdir- trick to descend further down.
717 Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
718 included in the top level makefile, and the kbuild infrastructure
719 is not operational at that point.
721 Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
722 be visited during "make clean".
724 === 6 Architecture Makefiles
726 The top level Makefile sets up the environment and does the preparation,
727 before starting to descend down in the individual directories.
728 The top level makefile contains the generic part, whereas
729 arch/$(ARCH)/Makefile contains what is required to set up kbuild
730 for said architecture.
731 To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
734 When kbuild executes, the following steps are followed (roughly):
735 1) Configuration of the kernel => produce .config
736 2) Store kernel version in include/linux/version.h
737 3) Symlink include/asm to include/asm-$(ARCH)
738 4) Updating all other prerequisites to the target prepare:
739 - Additional prerequisites are specified in arch/$(ARCH)/Makefile
740 5) Recursively descend down in all directories listed in
741 init-* core* drivers-* net-* libs-* and build all targets.
742 - The values of the above variables are expanded in arch/$(ARCH)/Makefile.
743 6) All object files are then linked and the resulting file vmlinux is
744 located at the root of the obj tree.
745 The very first objects linked are listed in head-y, assigned by
746 arch/$(ARCH)/Makefile.
747 7) Finally, the architecture specific part does any required post processing
748 and builds the final bootimage.
749 - This includes building boot records
750 - Preparing initrd images and thelike
753 --- 6.1 Set variables to tweak the build to the architecture
755 LDFLAGS Generic $(LD) options
757 Flags used for all invocations of the linker.
758 Often specifying the emulation is sufficient.
762 LDFLAGS := -m elf_s390
763 Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
764 the flags used. See chapter 7.
766 LDFLAGS_MODULE Options for $(LD) when linking modules
768 LDFLAGS_MODULE is used to set specific flags for $(LD) when
769 linking the .ko files used for modules.
770 Default is "-r", for relocatable output.
772 LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
774 LDFLAGS_vmlinux is used to specify additional flags to pass to
775 the linker when linking the final vmlinux image.
776 LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
780 LDFLAGS_vmlinux := -e stext
782 OBJCOPYFLAGS objcopy flags
784 When $(call if_changed,objcopy) is used to translate a .o file,
785 the flags specified in OBJCOPYFLAGS will be used.
786 $(call if_changed,objcopy) is often used to generate raw binaries on
791 OBJCOPYFLAGS := -O binary
793 #arch/s390/boot/Makefile
794 $(obj)/image: vmlinux FORCE
795 $(call if_changed,objcopy)
797 In this example, the binary $(obj)/image is a binary version of
798 vmlinux. The usage of $(call if_changed,xxx) will be described later.
800 AFLAGS $(AS) assembler flags
802 Default value - see top level Makefile
803 Append or modify as required per architecture.
806 #arch/sparc64/Makefile
807 AFLAGS += -m64 -mcpu=ultrasparc
809 CFLAGS $(CC) compiler flags
811 Default value - see top level Makefile
812 Append or modify as required per architecture.
814 Often, the CFLAGS variable depends on the configuration.
818 cflags-$(CONFIG_M386) += -march=i386
819 CFLAGS += $(cflags-y)
821 Many arch Makefiles dynamically run the target C compiler to
822 probe supported options:
827 cflags-$(CONFIG_MPENTIUMII) += $(call cc-option,\
828 -march=pentium2,-march=i686)
830 # Disable unit-at-a-time mode ...
831 CFLAGS += $(call cc-option,-fno-unit-at-a-time)
835 The first example utilises the trick that a config option expands
836 to 'y' when selected.
838 CFLAGS_KERNEL $(CC) options specific for built-in
840 $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
841 resident kernel code.
843 CFLAGS_MODULE $(CC) options specific for modules
845 $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
846 for loadable kernel modules.
849 --- 6.2 Add prerequisites to archprepare:
851 The archprepare: rule is used to list prerequisites that need to be
852 built before starting to descend down in the subdirectories.
853 This is usually used for header files containing assembler constants.
857 archprepare: maketools
859 In this example, the file target maketools will be processed
860 before descending down in the subdirectories.
861 See also chapter XXX-TODO that describe how kbuild supports
862 generating offset header files.
865 --- 6.3 List directories to visit when descending
867 An arch Makefile cooperates with the top Makefile to define variables
868 which specify how to build the vmlinux file. Note that there is no
869 corresponding arch-specific section for modules; the module-building
870 machinery is all architecture-independent.
873 head-y, init-y, core-y, libs-y, drivers-y, net-y
875 $(head-y) lists objects to be linked first in vmlinux.
876 $(libs-y) lists directories where a lib.a archive can be located.
877 The rest lists directories where a built-in.o object file can be
880 $(init-y) objects will be located after $(head-y).
881 Then the rest follows in this order:
882 $(core-y), $(libs-y), $(drivers-y) and $(net-y).
884 The top level Makefile defines values for all generic directories,
885 and arch/$(ARCH)/Makefile only adds architecture specific directories.
888 #arch/sparc64/Makefile
889 core-y += arch/sparc64/kernel/
890 libs-y += arch/sparc64/prom/ arch/sparc64/lib/
891 drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
894 --- 6.4 Architecture specific boot images
896 An arch Makefile specifies goals that take the vmlinux file, compress
897 it, wrap it in bootstrapping code, and copy the resulting files
898 somewhere. This includes various kinds of installation commands.
899 The actual goals are not standardized across architectures.
901 It is common to locate any additional processing in a boot/
902 directory below arch/$(ARCH)/.
904 Kbuild does not provide any smart way to support building a
905 target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
906 call make manually to build a target in boot/.
908 The recommended approach is to include shortcuts in
909 arch/$(ARCH)/Makefile, and use the full path when calling down
910 into the arch/$(ARCH)/boot/Makefile.
914 boot := arch/i386/boot
916 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
918 "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
919 make in a subdirectory.
921 There are no rules for naming architecture specific targets,
922 but executing "make help" will list all relevant targets.
923 To support this, $(archhelp) must be defined.
928 echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
931 When make is executed without arguments, the first goal encountered
932 will be built. In the top level Makefile the first goal present
934 An architecture shall always, per default, build a bootable image.
935 In "make help", the default goal is highlighted with a '*'.
936 Add a new prerequisite to all: to select a default goal different
943 When "make" is executed without arguments, bzImage will be built.
945 --- 6.5 Building non-kbuild targets
949 extra-y specify additional targets created in the current
950 directory, in addition to any targets specified by obj-*.
952 Listing all targets in extra-y is required for two purposes:
953 1) Enable kbuild to check changes in command lines
954 - When $(call if_changed,xxx) is used
955 2) kbuild knows what files to delete during "make clean"
958 #arch/i386/kernel/Makefile
959 extra-y := head.o init_task.o
961 In this example, extra-y is used to list object files that
962 shall be built, but shall not be linked as part of built-in.o.
965 --- 6.6 Commands useful for building a boot image
967 Kbuild provides a few macros that are useful when building a
972 if_changed is the infrastructure used for the following commands.
975 target: source(s) FORCE
976 $(call if_changed,ld/objcopy/gzip)
978 When the rule is evaluated, it is checked to see if any files
979 needs an update, or the command line has changed since the last
980 invocation. The latter will force a rebuild if any options
981 to the executable have changed.
982 Any target that utilises if_changed must be listed in $(targets),
983 otherwise the command line check will fail, and the target will
985 Assignments to $(targets) are without $(obj)/ prefix.
986 if_changed may be used in conjunction with custom commands as
987 defined in 6.7 "Custom kbuild commands".
989 Note: It is a typical mistake to forget the FORCE prerequisite.
990 Another common pitfall is that whitespace is sometimes
991 significant; for instance, the below will fail (note the extra space
993 target: source(s) FORCE
994 #WRONG!# $(call if_changed, ld/objcopy/gzip)
997 Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
1000 Copy binary. Uses OBJCOPYFLAGS usually specified in
1001 arch/$(ARCH)/Makefile.
1002 OBJCOPYFLAGS_$@ may be used to set additional options.
1005 Compress target. Use maximum compression to compress target.
1008 #arch/i386/boot/Makefile
1009 LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
1010 LDFLAGS_setup := -Ttext 0x0 -s --oformat binary -e begtext
1012 targets += setup setup.o bootsect bootsect.o
1013 $(obj)/setup $(obj)/bootsect: %: %.o FORCE
1014 $(call if_changed,ld)
1016 In this example, there are two possible targets, requiring different
1017 options to the linker. The linker options are specified using the
1018 LDFLAGS_$@ syntax - one for each potential target.
1019 $(targets) are assinged all potential targets, by which kbuild knows
1020 the targets and will:
1021 1) check for commandline changes
1022 2) delete target during make clean
1024 The ": %: %.o" part of the prerequisite is a shorthand that
1025 free us from listing the setup.o and bootsect.o files.
1026 Note: It is a common mistake to forget the "target :=" assignment,
1027 resulting in the target file being recompiled for no
1031 --- 6.7 Custom kbuild commands
1033 When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
1034 of a command is normally displayed.
1035 To enable this behaviour for custom commands kbuild requires
1036 two variables to be set:
1037 quiet_cmd_<command> - what shall be echoed
1038 cmd_<command> - the command to execute
1042 quiet_cmd_image = BUILD $@
1043 cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
1044 $(obj)/vmlinux.bin > $@
1047 $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
1048 $(call if_changed,image)
1049 @echo 'Kernel: $@ is ready'
1051 When updating the $(obj)/bzImage target, the line
1053 BUILD arch/i386/boot/bzImage
1055 will be displayed with "make KBUILD_VERBOSE=0".
1058 --- 6.8 Preprocessing linker scripts
1060 When the vmlinux image is built, the linker script
1061 arch/$(ARCH)/kernel/vmlinux.lds is used.
1062 The script is a preprocessed variant of the file vmlinux.lds.S
1063 located in the same directory.
1064 kbuild knows .lds files and includes a rule *lds.S -> *lds.
1067 #arch/i386/kernel/Makefile
1068 always := vmlinux.lds
1071 export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
1073 The assigment to $(always) is used to tell kbuild to build the
1075 The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
1076 specified options when building the target vmlinux.lds.
1078 When building the *.lds target, kbuild uses the variables:
1079 CPPFLAGS : Set in top-level Makefile
1080 EXTRA_CPPFLAGS : May be set in the kbuild makefile
1081 CPPFLAGS_$(@F) : Target specific flags.
1082 Note that the full filename is used in this
1085 The kbuild infrastructure for *lds file are used in several
1086 architecture specific files.
1089 === 7 Kbuild Variables
1091 The top Makefile exports the following variables:
1093 VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
1095 These variables define the current kernel version. A few arch
1096 Makefiles actually use these values directly; they should use
1097 $(KERNELRELEASE) instead.
1099 $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
1100 three-part version number, such as "2", "4", and "0". These three
1101 values are always numeric.
1103 $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
1104 or additional patches. It is usually some non-numeric string
1105 such as "-pre4", and is often blank.
1109 $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
1110 for constructing installation directory names or showing in
1111 version strings. Some arch Makefiles use it for this purpose.
1115 This variable defines the target architecture, such as "i386",
1116 "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
1117 determine which files to compile.
1119 By default, the top Makefile sets $(ARCH) to be the same as the
1120 host system architecture. For a cross build, a user may
1121 override the value of $(ARCH) on the command line:
1128 This variable defines a place for the arch Makefiles to install
1129 the resident kernel image and System.map file.
1130 Use this for architecture specific install targets.
1132 INSTALL_MOD_PATH, MODLIB
1134 $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
1135 installation. This variable is not defined in the Makefile but
1136 may be passed in by the user if desired.
1138 $(MODLIB) specifies the directory for module installation.
1139 The top Makefile defines $(MODLIB) to
1140 $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
1141 override this value on the command line if desired.
1145 If this variable is specified, will cause modules to be stripped
1146 after they are installed. If INSTALL_MOD_STRIP is '1', then the
1147 default option --strip-debug will be used. Otherwise,
1148 INSTALL_MOD_STRIP will used as the option(s) to the strip command.
1151 === 8 Makefile language
1153 The kernel Makefiles are designed to be run with GNU Make. The Makefiles
1154 use only the documented features of GNU Make, but they do use many
1157 GNU Make supports elementary list-processing functions. The kernel
1158 Makefiles use a novel style of list building and manipulation with few
1161 GNU Make has two assignment operators, ":=" and "=". ":=" performs
1162 immediate evaluation of the right-hand side and stores an actual string
1163 into the left-hand side. "=" is like a formula definition; it stores the
1164 right-hand side in an unevaluated form and then evaluates this form each
1165 time the left-hand side is used.
1167 There are some cases where "=" is appropriate. Usually, though, ":="
1168 is the right choice.
1172 Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
1173 Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
1174 Updates by Sam Ravnborg <sam@ravnborg.org>
1175 Language QA by Jan Engelhardt <jengelh@gmx.de>
1179 - Describe how kbuild supports shipped files with _shipped.
1180 - Generating offset header files.
1181 - Add more variables to section 7?